Datasheet > PI4MSD5V9546AZYEX

PI4MSD5V9546AZYEX

更新时间： 2025-08-07 19:21:19

品牌	Logo	应用领域
美台 - DIODES		/
页数	文件大小	规格书
14页	734K
描述
IC 4-CH BUS SWITCH 16TQFN

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中文翻译

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数据手册

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PI4MSD5V9546AZYEX 数据手册

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PI4MSD5V9546A

4 Channel I2C bus Switch with Reset

Features

Description

 1-of-4 bidirectional translating multiplexer

 I2C-bus interface logic

 Operating power supply voltage:1.65 V to 5.5 V

 Allows voltage level translation between 1.2V, 1.8V,2.5

V, 3.3 V and 5 V buses

The PI4MSD5V9546A is a quad bidirectional translating

switch controlled via the I2C bus. The SCL/SDA upstream

pair fans out to four downstream pairs, or channels. Any

individual SCx/SDx channel or combination of channels can

be selected, determined by the contents of the programmable

control register.

 Low standby current

 Low Ron switches

 Channel selection via I2C bus

An active LOW reset input allows the PI4MSD5V-9546A

to recover from a situation where one of the downstream

buses is stuck in a LOW state. Pulling the RESET pin LOW

resets the I2C bus state machine and causes all the channels to

be deselected as does the internal Power-On Reset (POR)

function.



Power-up with all multiplexer channels deselected

 Capacitance isolation when channel disabled

 No glitch on power-up

 Supports hot insertion

 5 V tolerant inputs

The pass gates of the switches are constructed such that the

VCC pin can be used to limit the maximum high voltage

which is passed by the PI4MSD5V9546A. This allows the use

of different bus voltages on each pair, so that1.2V, 1.8 V or

2.5 V or 3.3 V parts can communicate with 5 V parts without

any additional protection. External pull-up resistors pull the

bus up to the desired voltage level for each channel. All I/O

pins are 5 V tolerant.

 0 Hz to 400 kHz clock frequency

 ESD protection exceeds 8000 V HBM per JESD22-

A114, and 1000 V CDM per JESD22-C101

 Latch-up testing is done to JEDEC Standard JESD78

which exceeds 100 mA



Packages offered: SOIC-16W,TSSOP-16L, TQFN4*4-

16ZY

Pin Configuration

Pin Description

Pin No.

(TSSOP,

SOIC)

Pin No.

(TQFN)

Name

Type

Description

Input

address input 0

address input 1

TSSOP

SOIC

active LOW reset

Input

RESET

SD0

SC0

SD1

SC1

GND

SD2

SC2

SD3

SC3

I/O

serial data 0

serial clock 0

serial data 1

I/O

serial clock 1

supply ground

serial data 2

Ground

I/O

serial clock 2

serial data 3

I/O

TQFN

I/O

serial clock 3

address input 2

serial clock line

serial data line

supply voltage

Input

I/O

SCL

SDA

VCC

I/O

Power

All trademarks are property of their respective owners.

2017-01-0005

www.diodes.com

1/18/2017

PT0527-5

12 3 4 5 6 7...14

中文翻译

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