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PI2EQX6874

更新时间： 2024-09-16 14:54:15
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美台 - DIODES /
页数 文件大小 规格书
22页 1842K
描述
1.2V, 6.5Gbps 4-lane/8-channel SAS2/SATA/XAUI ReDriver with Individual Channel I2C Control

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PI2EQX6874 数据手册

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PI2EQX6874  
6.5Gbps 4-Lane SAS2/SATA3/XAUI ReDriver™with  
Equalization,De-emphasis and Flow-through pinout  
Features  
Description  
ꢀÎUp to 6.5Gbps SAS2/SATA3/XAUI ReDriver  
Pericom Semiconductor’s PI2EQX6874 is a 6.5Gbps low  
power, 4 lane (8-channel) SAS2, SATA3, XAUI signal ReDriver.  
e device provides programmable equalization, amplifi-  
ꢀÎSupporting 8 differential channels or 4 lanes  
2
ꢀÎPer channel I C configuration controls (3.3V Tolerant)  
ꢀÎAdjustable receiver equalization  
ꢀÎAdjustable transmitter amplitude and de-emphasis  
ꢀÎ50-Ohm input/output termination  
ꢀÎMux/Demux feature  
2
cation, and de-emphasis by I C control, to optimize per-  
formance over a variety of physical mediums by reducing  
Inter-symbol interference.  
PI2EQX6874 supports eight 100-Ohm Differential CML data  
I/O’s between the Protocol ASIC to a switch fabric, across a back-  
plane, or extends the signals across other distant data pathways  
on the user’s platform.  
ꢀÎChannel loop-back  
ꢀÎOOB fully supported  
e integrated equalization circuitry provides flexibility with  
signal integrity of the signal before the ReDriver, whereas the  
integrated de-emphasis circuitry provides flexibility with signal  
integrity of the signal aꢀer the ReDriver.  
ꢀÎSingle supply voltage, 1.2V 5%  
ꢀÎActive Current per channel - 95mA (typical)  
ꢀÎPower down modes  
à Slumber current per channel -10mA (typical)  
à Standby current -1mA (typical)  
ꢀÎIndustrial temperature range: -40°C to 85°C  
In addition to providing signal re-conditioning, Pericom’s  
PI2EQX6874 also provides power management Stand-by mode  
2
operated by a Power Down pin, or through I C register. When  
input is idle, the device goes into power saving Slumber mode.  
ꢀÎPackaging: 56-contact TQFN (5mm x 11mm)  
Pin Configuration (Top-Side View)  
Block Diagram  
+
Output  
Controls  
Input�level�detect  
to�control�logic  
−
51 50  
53  
56 55 54  
1
52  
49  
48  
47  
46  
45  
+
xyRx+  
xyRx-  
A0TX+  
A0TX-  
VDD  
A0RX+  
A0RX-  
B0TX+  
xyTx+  
xyTx-  
+
2
3
4
−
Equalizer  
−
B0RX+  
B0RX-  
VDD  
5
B0TX-  
44  
43  
42  
41  
A
B
xyTx+  
xyTx-  
+
Equalizer  
xyRx+  
xyRx-  
A1TX+  
A1TX-  
6
7
+
VDD  
A1RX+  
−
−
8
A1RX-  
B1RX-  
B1RX+  
Input�level�detect  
to�control�logic  
Output  
Controls  
+
9
10  
B1TX-  
B1TX+  
40  
39  
−
VDD  
A2TX+  
A2TX-  
11  
12  
13  
14  
15  
VDD  
A2RX+  
A2RX-  
B2TX-  
B2TX+  
38  
37  
36  
35  
34  
33  
Data�Lane�Repeats�4�Times  
SELy_x  
Sy_x  
B2RX-  
B2RX+  
VDD  
Mode  
LB#  
Control�Registers  
&�Logic  
Dy_x  
16  
A3TX+  
A3TX-  
VDD  
PRE_x  
17  
18  
A3RX+  
A3RX-  
32  
31  
B3RX+  
B3RX-  
Power  
PD#  
19  
20  
Management  
B3TX+  
B3TX-  
30  
VDD  
29  
28  
26 27  
25  
24  
21 22 23  
SDA  
SCL  
I2C�Control  
Ax  
All trademarks are property of their respective owners.  
www.pericom.com  
12/22/15  
15-0181  
1
1234567...22

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