A product Line of
Diodes Incorporated
PI2EQX6812
6.5Gbps 2-Lane (4-channel)SAS2/SATA/XAUI ReDriver™ with Equalization & De-emphasis
Features
Description
ꢀÎUp to 6.5Gbps SAS2/SATA/XAUI ReDriver™
ꢀÎSupporting 4 differential channels or 2 lane
ꢀÎIndependent channel configuration
Pericom Semiconductor’s PI2EQX6812 is a low power, SAS2,
2-lane (4 differential channels) SATA, XAUI signal ReDriver™.
e device provides programmable equalization, amplification,
2
and de-emphasis by either pin strapping option or I C Control,
2
ꢀÎPin strap and I C configuration controls (3.3V Tolerant)
to optimize performance over a variety of physical mediums by
reducing Inter-symbol interference.
ꢀÎAdjustable receiver equalization
ꢀÎAdjustable transmitter amplitude and de-emphasis
ꢀÎAdjustable input threshold level
ꢀÎ50-Ohm input/output termination
ꢀÎMux/Demux and loop-back features
ꢀÎOOB fully supported
ꢀÎSingle supply voltage, 1.2V 5%
ꢀÎActive current per channel -95mA (typical)
ꢀÎPower down standby mode
PI2EQX6812 supports four 100-Ohm Differential CML data I/O’s
between the Protocol ASIC to a switch fabric, across a backplane,
or extends the signals across other distant data pathways on the
user’s platform.
e integrated equalization circuitry provides flexibility with
signal integrity of the signal before the ReDriver, whereas the
integrated de-emphasis circuitry provides flexibility with signal
integrity of the signal aꢀer the ReDriver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX6812 also provides power management Stand-by mode
à Standby current -1mA (typical)
ꢀÎAutomatic slumber mode power savings
2
operated by a Power Down pin, or through I C register. When
à Slumber current per channel -10mA (typical)
the input is idle, the device goes to power saving slumber mode
o
o
ꢀÎIndustrial operating temperature range: -40 C to 85 C
ꢀÎPackaging (Pb-free & Green):
à 42-contact TQFN (9mm x3.5mm)
Pin Configuration (Top-Side View)
Block Diagram
+
Output
Controls
Input�level�detect
to�control�logic
−
+
xyRx+
xyRx-
39
42 41 40
xyTx+
xyTx-
+
SEL1A
NC
1
2
3
4
38
37
36
35
34
33
32
31
SDA
PD#
−
Equalizer
Channel A0-1
−
VDD
VDD
A0TX+
Equalizer
A0RX+
xyTx+
xyTx-
+
xyRx+
xyRx-
+
A0RX-
B0TX+
B0TX-
VDD
5
6
7
A0TX-
B0RX+
B0RX-
VDD
−
−
Input�level�detect
to�control�logic
+
Output
Controls
−
8
Channels B0-1
VDD
A1RX+
9
10
VDD
30
29
A1TX+
A1TX-
B1RX+
A1RX-
B1TX+
B1TX-
VDD
11
12
13
14
15
16
17
28
27
26
25
24
23
22
SELy_x
Dy_x
Mode
Control�Registers
&�Logic
B1RX-
VDD
SEL1B
MODE
D2_B
A4
SEL2B
A1
Power
PD#
Management
21
18 19 20
SDA
SCL
I2C�Control
Ax
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www.diodes.com
07/14/16
16-0124
1