SE5537

更新时间： 2024-02-11 08:14:24

品牌	Logo	应用领域
恩智浦 - NXP		放大器
页数	文件大小	规格书
8页	107K
描述
Sample-and-hold amplifier

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技术参数
数据手册

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SE5537 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
放大器类型：	SAMPLE AND HOLD CIRCUIT	JESD-30 代码：	R-PDIP-T8
JESD-609代码：	e0	标称负供电电压 (Vsup)：	-15 V
功能数量：	1	端子数量：	8
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	+-15 V
子类别：	Sample and Hold Circuits	标称供电电压 (Vsup)：	15 V
表面贴装：	NO	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
Base Number Matches：	1

SE5537 数据手册

Philips Semiconductors Linear Products

Product specification

Sample-and-hold amplifier

NE/SE5537

DESCRIPTION

PIN CONFIGURATIONS

The NE5537 monolithic sample-and-hold amplifier combines the

best features of ion-implanted JFETs with bipolar devices to obtain

high accuracy, fast acquisition time, and low droop rate. This device

is pin-compatible with the LF198, and features superior performance

in droop rate and output drive capability. The circuit shown in Figure

1 contains two operational amplifiers which function as a unity gain

amplifier in the sample mode. The first amplifier has bipolar input

transistors which give the system a low offset voltage. The second

amplifier has JFET input transistors to achieve low leakage current

from the hold capacitor. A unique circuit design for leakage current

cancellation using current mirrors gives the NE5537 a low droop

rate at higher temperature. The output stage has the capability to

drive a 2kΩ load. The logic input is compatible with TTL, PMOS or

CMOS logic. The differential logic threshold is 1.4V with the sample

mode occurring when the logic input is high. It is available in 8-lead

TO-5, 8-pin plastic DIP packages, and 14-pin SO packages.

FE and N Packages

V+

LOGIC

OFFSET ADJUST

LOGIC REFERENCE

INPUT

V–

OUTPUT

D Package

ADJ

INPUT

V+

V–

LOGIC

LOGIC REFERENCE

FEATURES

• Operates from ±5V to ±18V supplies

OUTPUT

NOTE:

• Hold leakage current 6pA @ T = 25°C

1. SO and non-standard pinouts.

• Less than 4µs acquisition time

• TTL, PMOS, CMOS compatible logic input

• 0.5mV typical hold step at CH=0.01µF

• Low input offset: 1MV (typical)

BLOCK DIAGRAM

OFFSET

• 0.002% gain accuracy with R =2kΩ

30k

• Low output noise in hold mode

• Input characteristics do not change during hold mode

• High supply rejection ratio in sample or hold

• Wide bandwidth

–

OUTPUT

INPUT

LOGIC

300

–

LOGIC

REFERENCE

HOLD

CAPACITOR

ORDERING INFORMATION

DESCRIPTION

TEMPERATURE RANGE

0 to +70°C

ORDER CODE

NE5537N

DWG #

8-Pin Plastic Dual In-Line Package (DIP)

14-Pin Plastic Small Outline (SO) Package

8-Pin Plastic Dual In-Line Package (DIP)

0404B

0175D

0404B

0 to +70°C

NE5537D

-55°C to +125°C

SE5537FE

884

August 31, 1994

853-1044 13721

12 3 4 5 6 7 8

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与SE5537相关器件

型号	品牌	描述	获取价格	数据表
SE5537FE	NXP	Sample-and-hold amplifier	获取价格
SE5537H	PHILIPS	Sample and Hold Circuit, 1 Func, MBCY8	获取价格
SE5537N-A	PHILIPS	Sample and Hold Circuit, 1 Func, PDIP8	获取价格
SE5537NSIIB	PHILIPS	Sample and Hold Circuit, 1 Func, PDIP8	获取价格
SE5538F	NXP	IC DUAL OP-AMP, 3000 uV OFFSET-MAX, 6 MHz BAND WIDTH, CDIP14, Operational Amplifier	获取价格
SE5538K	NXP	IC DUAL OP-AMP, 3000 uV OFFSET-MAX, 6 MHz BAND WIDTH, MBCY8, Operational Amplifier	获取价格

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