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74HC193NB PDF预览

74HC193NB

更新时间: 2024-02-04 20:48:20
品牌 Logo 应用领域
恩智浦 - NXP 计数器
页数 文件大小 规格书
30页 184K
描述
HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDIP16

74HC193NB 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.59
逻辑集成电路类型:BINARY COUNTER峰值回流温度(摄氏度):NOT SPECIFIED
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

74HC193NB 数据手册

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74HC193; 74HCT193  
Presettable synchronous 4-bit binary up/down counter  
Rev. 4 — 24 June 2013  
Product data sheet  
1. General description  
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate  
up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state  
synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is  
pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while  
CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at  
any time to guarantee predictable behaviour. The device can be cleared at any time by the  
asynchronous master reset input (MR); it may also be loaded in parallel by activating the  
asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count  
down (TCD) outputs are normally HIGH. When the circuit has reached the maximum  
count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.  
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,  
the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.  
The terminal count outputs can be used as the clock input signals to the next higher order  
circuit in a multistage counter, since they duplicate the clock waveforms. Multistage  
counters will not be fully synchronous, since there is a slight delay time difference added  
for each stage that is added. The counter may be preset by the asynchronous parallel  
load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is  
loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the  
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on  
the master reset (MR) input will disable the parallel load gates, override both clock inputs  
and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a  
reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted  
as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the  
use of current limiting resistors to interface inputs to voltages in excess of VCC  
.
2. Features and benefits  
Input levels:  
For 74HC193: CMOS level  
For 74HCT193: TTL level  
Synchronous reversible 4-bit binary counting  
Asynchronous parallel load  
Asynchronous reset  
Expandable without external logic  
Complies with JEDEC standard no. 7A  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V.  

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