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74AUP1G3208 PDF预览

74AUP1G3208

更新时间: 2024-01-07 12:45:56
品牌 Logo 应用领域
恩智浦 - NXP 线路驱动器或接收器驱动程序和接口接口集成电路
页数 文件大小 规格书
19页 71K
描述
Low-power 3-input OR-AND gate

74AUP1G3208 技术参数

生命周期:Active包装说明:HVBCC,
Reach Compliance Code:compliant风险等级:1.6
系列:AUP/ULP/VJESD-30 代码:R-PBCC-B6
长度:1 mm逻辑集成电路类型:OR-AND GATE
湿度敏感等级:1功能数量:1
输入次数:3端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:HVBCC
封装形状:RECTANGULAR封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):20.1 ns
座面最大高度:0.35 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):0.8 V标称供电电压 (Vsup):1.1 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:BUTT
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:0.8 mmBase Number Matches:1

74AUP1G3208 数据手册

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74AUP1G3208  
Low-power 3-input OR-AND gate  
Rev. 01.00 — 17 January 2006  
Preliminary data sheet  
1. General description  
The 74AUP1G3208 is a high-performance, low-power, low-voltage, Si-gate CMOS device,  
superior to most advanced CMOS compatible TTL families.  
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall  
times across the entire VCC range from 0.8 V to 3.6 V.  
This device ensures a very low static and dynamic power consumption across the entire  
VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial Power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
The 74AUP1G3208 provides the Boolean function: Y = (A + B) × C. The user can choose  
the logic functions OR, AND and OR-AND. All inputs can be connected to VCC or GND.  
2. Features  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114-C Class 3A. Exceeds 5000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101-C exceeds 1000 V  
Low static power consumption; ICC = 0.9 µA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  

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