5秒后页面跳转
74AUP1G175GW PDF预览

74AUP1G175GW

更新时间: 2024-01-01 10:50:42
品牌 Logo 应用领域
恩智浦 - NXP 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
26页 92K
描述
Low-power D-type flip-flop with reset; positive-edge trigger

74AUP1G175GW 技术参数

Source Url Status Check Date:2013-06-14 00:00:00是否无铅: 含铅
是否Rohs认证: 符合生命周期:Active
Reach Compliance Code:unknown风险等级:5.72
Base Number Matches:1

74AUP1G175GW 数据手册

 浏览型号74AUP1G175GW的Datasheet PDF文件第2页浏览型号74AUP1G175GW的Datasheet PDF文件第3页浏览型号74AUP1G175GW的Datasheet PDF文件第4页浏览型号74AUP1G175GW的Datasheet PDF文件第5页浏览型号74AUP1G175GW的Datasheet PDF文件第6页浏览型号74AUP1G175GW的Datasheet PDF文件第7页 
74AUP1G175  
Low-power D-type flip-flop with reset; positive-edge trigger  
Rev. 01.mm — 27 March 2006  
Preliminary data sheet  
1. General description  
The 74AUP1G175 is a high-performance, low-power, low-voltage, Si-gate CMOS device,  
superior to most advanced CMOS compatible TTL families.  
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall  
times across the entire VCC range from 0.8 V to 3.6 V.  
This device ensures a very low static and dynamic power consumption across the entire  
VCC range from 0.8 V to 3.6 V.  
This device is fully specified for partial Power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual  
data (D) input, clock (CP) input, master reset (MR) input, and Q output.The master reset  
(MR) is an asynchronous active LOW input and operates independently of the clock input.  
Information on the data input is transferred to the Q output on the LOW-to-HIGH transition  
of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH  
clock transition, for predictable operation.  
2. Features  
Wide supply voltage range from 0.8 V to 3.6 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-12 (0.8 V to 1.3 V)  
JESD8-11 (0.9 V to 1.65 V)  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8-B (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114-C Class 3A. Exceeds 5000 V  
MM JESD22-A115-A exceeds 200 V  
CDM JESD22-C101-C exceeds 1000 V  
Low static power consumption; ICC = 0.9 µA (maximum)  
Latch-up performance exceeds 100 mA per JESD 78 Class II  
Inputs accept voltages up to 3.6 V  
Low noise overshoot and undershoot < 10 % of VCC  
IOFF circuitry provides partial Power-down mode operation  

与74AUP1G175GW相关器件

型号 品牌 描述 获取价格 数据表
74AUP1G175GW-G NXP Low-power D-type flip-flop with reset; positive-edge trigger

获取价格

74AUP1G175GW-Q100 NXP AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO6, PLASTIC, SC-88,

获取价格

74AUP1G175GW-Q100 NEXPERIA Low-power D-type flip-flop with reset; positive-edge triggerProduction

获取价格

74AUP1G175GW-Q100H NXP 74AUP1G175-Q100 - Low-power D-type flip-flop with reset; positive-edge trigger TSSOP 6-Pin

获取价格

74AUP1G17FW4-7 DIODES SINGLE SCHMITT-TRIGGER BUFFER

获取价格

74AUP1G17FW5-7 DIODES Buffer, AUP/ULP/V Series, 1-Func, 1-Input, CMOS, PDSO6, 1 X 1 MM, 0.50 MM HEIGHT, 0.35 MM

获取价格