5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 触发器/锁存器> 74ABT5074N
74ABT5074N PDF预览

74ABT5074N

更新时间： 2024-02-22 16:58:01
品牌 Logo 应用领域
恩智浦 - NXP 触发器锁存器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
7页 104K
描述
Synchronizing dual D-type flip-flop with metastable immune characteristics

阅读下载

获取价格

74ABT5074N 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：PLASTIC, TSSOP1-14针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
其他特性：WITH METASTABLE IMMUNE CHARACTERISTICS系列：ABT
JESD-30 代码：R-PDSO-G14长度：5 mm
逻辑集成电路类型：D FLIP-FLOP位数：1
功能数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：4.5 ns
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：150 MHz
Base Number Matches：1

74ABT5074N 数据手册

 浏览型号74ABT5074N的Datasheet PDF文件第2页浏览型号74ABT5074N的Datasheet PDF文件第3页浏览型号74ABT5074N的Datasheet PDF文件第4页浏览型号74ABT5074N的Datasheet PDF文件第5页浏览型号74ABT5074N的Datasheet PDF文件第6页浏览型号74ABT5074N的Datasheet PDF文件第7页 
Philips Semiconductors Advanced BiCMOS Products  
Product specification  
Synchronizing dual D-type flip-flop  
with metastable immune characteristics  
74ABT5074  
FEATURES  
PIN CONFIGURATION  
• Metastable immune characteristics  
RD0  
D0  
1
2
3
4
5
14  
V
CC  
• Pin compatible with 74F74 and 74F5074  
13 RD1  
12 D1  
• Typical f  
= 200MHz  
MAX  
CP0  
SD0  
Q0  
• Output skew guaranteed less than 2.0ns  
11 CP1  
10 SD1  
• High source current (I = 15mA) ideal for clock driver  
OH  
applications  
Q0  
6
7
9
8
Q1  
Q1  
• Output capability: +20mA/–15mA  
• Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17  
GND  
SA00001  
• ESD protection exceeds 2000V per MIL STD 883 Method 3015  
and 200V per Machine Model  
PIN DESCRIPTION  
PIN NUMBER  
2, 12  
SYMBOL  
NAME AND FUNCTION  
Data inputs  
DESCRIPTION  
D0, D1  
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop  
featuring individual data, clock, set and reset inputs; also true and  
complementary outputs.  
3, 11  
CP0, CP1 Clock inputs (active rising edge)  
SD0, SD1 Set inputs (active-Low)  
4, 10  
Set (SDn) and reset (RDn) are asynchronous active low inputs and  
operate independently of the clock (CPn) input. Data must be stable  
just one setup time prior to the low-to-high transition of the clock for  
guaranteed propagation delays.  
1, 13  
RD0, RD1 Reset inputs (active-Low)  
Data outputs (active-Low),  
non-inverting  
5, 9  
6, 8  
Q0, Q1  
Clock triggering occurs at a voltage level and is not directly related  
to the transition time of the positive-going pulse. Following the hold  
time interval, data at the Dn input may be changed without affecting  
the levels of the output.  
Data outputs (active-Low),  
inverting  
Q0, Q1  
7
GND  
Ground (0V)  
The 74ABT5074 is designed so that the outputs can never display a  
metastable state due to setup and hold time violations. If setup time  
and hold time are violated the propagation delays may be extended  
beyond the specifications but the outputs will not glitch or display a  
metastable state. Typical metastability parameters for the  
74ABT5074 are:  
14  
V
CC  
Positive supply voltage  
7
τ
94ps and T 1.3 × 10 sec  
o
where τ represents a function of the rate at which a latch in a  
metastable state resolves that condition and T represents a  
0
function of the measurement of the propensity of a latch to enter a  
metastable state.  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C; GND = 0V  
SYMBOL  
PARAMETER  
TYPICAL  
UNIT  
T
amb  
t
t
Propagation delay  
2.8  
2.4  
PLH  
PHL  
C = 50pF; V = 5V  
ns  
L
CC  
CPn to Qn or Qn  
Input capacitance  
Total supply current  
C
V = 0V or V  
I CC  
3
2
pF  
IN  
I
Outputs disabled; V =5.5V  
µA  
CC  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE  
–40°C to +85°C  
ORDER CODE  
74ABT5074N  
74ABT5074D  
74ABT5074DB  
74ABT5074PW  
DRAWING NUMBER  
SOT27-1  
14-pin plastic DIP  
14-pin plastic SOL  
–40°C to +85°C  
SOT108-1  
14-pin plastic shrink small outline SSOP Type II  
14-pin plastic thin shrink small outline (TSSOP) Type I  
–40°C to +85°C  
SOT337-1  
–40°C to +85°C  
SOT402-1  
1
December 15, 1994  
853-1775 14470  
1234567

下载PDF

与74ABT5074N相关器件

型号 品牌 描述 获取价格 数据表
74ABT5074PW NXP Synchronizing dual D-type flip-flop with metastable immune characteristics

获取价格
74ABT5074PWDH NXP 暂无描述

获取价格
74ABT5074PW-T ETC Dual D-Type Flip-Flop

获取价格
74ABT534A NXP Octal D-type flip-flop, inverting 3-State

获取价格
74ABT534A INFINEON Octal D-type flip-flop, inverting (3-State)

获取价格
74ABT534AD NXP Octal D-type flip-flop, inverting 3-State

获取价格

与74ABT5074N相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证