Philips Semiconductors Advanced BiCMOS Products
Product specification
Synchronizing dual D-type flip-flop
with metastable immune characteristics
74ABT5074
FEATURES
PIN CONFIGURATION
• Metastable immune characteristics
RD0
D0
1
2
3
4
5
14
V
CC
• Pin compatible with 74F74 and 74F5074
13 RD1
12 D1
• Typical f
= 200MHz
MAX
CP0
SD0
Q0
• Output skew guaranteed less than 2.0ns
11 CP1
10 SD1
• High source current (I = 15mA) ideal for clock driver
OH
applications
Q0
6
7
9
8
Q1
Q1
• Output capability: +20mA/–15mA
• Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
GND
SA00001
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
PIN DESCRIPTION
PIN NUMBER
2, 12
SYMBOL
NAME AND FUNCTION
Data inputs
DESCRIPTION
D0, D1
The 74ABT5074 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set and reset inputs; also true and
complementary outputs.
3, 11
CP0, CP1 Clock inputs (active rising edge)
SD0, SD1 Set inputs (active-Low)
4, 10
Set (SDn) and reset (RDn) are asynchronous active low inputs and
operate independently of the clock (CPn) input. Data must be stable
just one setup time prior to the low-to-high transition of the clock for
guaranteed propagation delays.
1, 13
RD0, RD1 Reset inputs (active-Low)
Data outputs (active-Low),
non-inverting
5, 9
6, 8
Q0, Q1
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive-going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
Data outputs (active-Low),
inverting
Q0, Q1
7
GND
Ground (0V)
The 74ABT5074 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the
74ABT5074 are:
14
V
CC
Positive supply voltage
7
τ
94ps and T 1.3 × 10 sec
o
where τ represents a function of the rate at which a latch in a
metastable state resolves that condition and T represents a
0
function of the measurement of the propensity of a latch to enter a
metastable state.
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
2.8
2.4
PLH
PHL
C = 50pF; V = 5V
ns
L
CC
CPn to Qn or Qn
Input capacitance
Total supply current
C
V = 0V or V
I CC
3
2
pF
IN
I
Outputs disabled; V =5.5V
µA
CC
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40°C to +85°C
ORDER CODE
74ABT5074N
74ABT5074D
74ABT5074DB
74ABT5074PW
DRAWING NUMBER
SOT27-1
14-pin plastic DIP
14-pin plastic SOL
–40°C to +85°C
SOT108-1
14-pin plastic shrink small outline SSOP Type II
14-pin plastic thin shrink small outline (TSSOP) Type I
–40°C to +85°C
SOT337-1
–40°C to +85°C
SOT402-1
1
December 15, 1994
853-1775 14470