5秒后页面跳转
捷配首页

Datasheet > 可编程逻辑 > 可编程逻辑器件> PEEL22LV10AZT-25
PEEL22LV10AZT-25 PDF预览

PEEL22LV10AZT-25

更新时间： 2024-11-16 07:03:35
品牌 Logo 应用领域
易亨 - ANACHIP /
页数 文件大小 规格书
10页 683K
描述
CMOS Programmable Electrically Erasable Logic Device

阅读下载

中文翻译

获取价格

PEEL22LV10AZT-25 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：TSSOP, TSSOP24,.25Reach Compliance Code：unknown
风险等级：5.92架构：PAL-TYPE
最大时钟频率：33.3 MHzJESD-30 代码：R-PDSO-G24
JESD-609代码：e0输入次数：22
输出次数：10产品条款数：133
端子数量：24最高工作温度：70 °C
最低工作温度：输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：3/3.3 V
可编程逻辑类型：EE PLD传播延迟：25 ns
认证状态：Not Qualified子类别：Programmable Logic Devices
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL

PEEL22LV10AZT-25 数据手册

 浏览型号PEEL22LV10AZT-25的Datasheet PDF文件第2页浏览型号PEEL22LV10AZT-25的Datasheet PDF文件第3页浏览型号PEEL22LV10AZT-25的Datasheet PDF文件第4页浏览型号PEEL22LV10AZT-25的Datasheet PDF文件第5页浏览型号PEEL22LV10AZT-25的Datasheet PDF文件第6页浏览型号PEEL22LV10AZT-25的Datasheet PDF文件第7页 
PEEL™ 22LV10AZ-25  
CMOS Programmable Electrically Erasable Logic Device  
Features  
Low Voltage, Ultra Low Power Operation  
Architectural Flexibility  
- Vcc = 2.7 to 3.6 V  
-
Enhanced architecture fits in more logic  
- Icc = 5 µA (typical) at standby  
3- 133 product terms x 44 input AND array  
- Icc = 1.5 mA (typical) at 1 MHz  
- Meets JEDEC LV Interface Spec (JESD8-A)  
- 5 Volt tolerant inputs and I/O’s  
-
-
-
-
-
-
-
-
12 inputs and 10 I/O pins  
12 possible macrocell configurations  
Asynchronous clear, synchronous preset  
Independent output enables  
CMOS Electrically Erasable Technology  
- Superior factory testing  
Programmable clock; pin 1 or p-term  
Programmable clock polarity  
24 Pin DIP/SOIC/TSSOP and 28 Pin PLCC  
Schmitt triggers on clock and data inputs  
-
Reprogrammable in plastic package  
-
Reduces retrofit and development costs  
Application Versatility  
-
-
-
-
-
Replaces random logic  
Schmitt Trigger Inputs  
Super set of standard PLDs  
-
Eliminates external Schmitt trigger devices  
Pin and JEDEC compatible with 22V10  
Ideal for battery powered systems  
Replaces expensive oscillators  
- Ideal for encoder designs  
General Description  
The PEEL™22LV10AZ is a Programmable Electrically Erasable  
Logic (PEEL™) SPLD (Simple Programmable Logic Device) that  
operates over the supply voltage range of 2.7V-3.6V and fea- tures  
ultra-low, automatic “zero” power-down operation. The  
PEEL™22LV10AZ is logically and functionally similar to Ana-  
chip’s 5V PEEL™22CV10A+ and PEEL™22CV10AZ. The  
“zero power” (50 µA max. Icc) power-down mode makes the  
PEEL™22LV10AZ ideal for a broad range of battery-powered  
portable equipment applications, from hand-held meters to PCM-  
CIA modems. EE-reprogrammability provides both the conve-  
nience of fast reprogramming for product development and quick  
product personalization in manufacturing, including Engineering  
Change Orders.  
The differences between the PEEL™22LV10AZ and  
PEEL™22CV10A include the addition of programmable clock  
polarity, p-term clock, and Schmitt trigger input buffers on all  
inputs, including the clock. Schmitt trigger inputs allow direct  
input of slow signals such as biomedical and sine waves or  
clocks. Like the PEEL™22CV10, the PEEL™22LV10AZ is a pin  
and JEDEC compatible, logical superset of the industry stan- dard  
PAL22V10 SPLD (Figure 26). The PEEL™22LV10AZ pro- vides  
additional architectural features that allow more logic to be  
incorporated into the design. The PEEL™22LV10AZ architec-  
ture allows it to replace over twenty standard 24-pin DIP, SOIC,  
TSSOP and PLCC packages.  
Figure 26 Block Diagram  
Figure 26 Pin Configuration  
I/CLK  
1
24  
VCC  
I
I
2
23  
22  
I/O  
I/O  
3
I
I
4
5
21  
20  
I/O  
I/O  
I/O  
I/O  
™
19  
I
I
6
7
18  
17  
16  
15  
I
I
I
8
I/O  
I/O  
I/O  
9
10  
I
11  
12  
14  
13  
I/O  
I
GND  
TSSOP  
DIP  
PLCC  
SOIC  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent  
accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/10  
1234567...10

中文翻译

下载PDF

与PEEL22LV10AZT-25相关器件

型号 品牌 获取价格 描述 数据表
PEEL22LV10AZT-25L ANACHIP

获取价格

 		CMOS Programmable Electrically Erasable Logic Device
PEEL22LV10AZT-25L ICT

获取价格

 		EE PLD, 25ns, CMOS, PDSO24, 0.170 INCH, LEAD FREE, TSSOP-24
PEEL22LV10AZT-35 ETC

获取价格

 		CMOS Programmable Electrically Erasable Logic Device
PEEL22LV10AZTI-25 ETC

获取价格

 		CMOS Programmable Electrically Erasable Logic Device
PEEL22LV10AZTI-35 ETC

获取价格

 		ASIC
PEEL22V10AZ3J15 ETC

获取价格

 		ASIC
PEEL22V10AZ3J-15 ICT

获取价格

 		EE PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28
PEEL22V10AZ3J25 ETC

获取价格

 		ASIC
PEEL22V10AZ3J-25 ICT

获取价格

 		EE PLD, 25ns, CMOS, PQCC28, PLASTIC, LCC-28
PEEL22V10AZ3P15 ETC

获取价格

 		ASIC

与PEEL22LV10AZT-25相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证