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PEEL22LV10AZJ-25L

更新时间： 2024-09-29 07:03:35
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易亨 - ANACHIP 可编程逻辑器件时钟
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10页 683K
描述
CMOS Programmable Electrically Erasable Logic Device

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PEEL22LV10AZJ-25L 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：QCCJ, LDCC28,.5SQReach Compliance Code：unknown
风险等级：5.8Is Samacsys：N
架构：PAL-TYPE最大时钟频率：33.3 MHz
JESD-30 代码：S-PQCC-J28输入次数：22
输出次数：10产品条款数：133
端子数量：28最高工作温度：70 °C
最低工作温度：输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC28,.5SQ封装形状：SQUARE
封装形式：CHIP CARRIER电源：3/3.3 V
可编程逻辑类型：EE PLD传播延迟：25 ns
认证状态：Not Qualified子类别：Programmable Logic Devices
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
Base Number Matches：1

PEEL22LV10AZJ-25L 数据手册

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PEEL™ 22LV10AZ-25  
CMOS Programmable Electrically Erasable Logic Device  
Features  
Low Voltage, Ultra Low Power Operation  
Architectural Flexibility  
- Vcc = 2.7 to 3.6 V  
-
Enhanced architecture fits in more logic  
- Icc = 5 µA (typical) at standby  
3- 133 product terms x 44 input AND array  
- Icc = 1.5 mA (typical) at 1 MHz  
- Meets JEDEC LV Interface Spec (JESD8-A)  
- 5 Volt tolerant inputs and I/O’s  
-
-
-
-
-
-
-
-
12 inputs and 10 I/O pins  
12 possible macrocell configurations  
Asynchronous clear, synchronous preset  
Independent output enables  
CMOS Electrically Erasable Technology  
- Superior factory testing  
Programmable clock; pin 1 or p-term  
Programmable clock polarity  
24 Pin DIP/SOIC/TSSOP and 28 Pin PLCC  
Schmitt triggers on clock and data inputs  
-
Reprogrammable in plastic package  
-
Reduces retrofit and development costs  
Application Versatility  
-
-
-
-
-
Replaces random logic  
Schmitt Trigger Inputs  
Super set of standard PLDs  
-
Eliminates external Schmitt trigger devices  
Pin and JEDEC compatible with 22V10  
Ideal for battery powered systems  
Replaces expensive oscillators  
- Ideal for encoder designs  
General Description  
The PEEL™22LV10AZ is a Programmable Electrically Erasable  
Logic (PEEL™) SPLD (Simple Programmable Logic Device) that  
operates over the supply voltage range of 2.7V-3.6V and fea- tures  
ultra-low, automatic “zero” power-down operation. The  
PEEL™22LV10AZ is logically and functionally similar to Ana-  
chip’s 5V PEEL™22CV10A+ and PEEL™22CV10AZ. The  
“zero power” (50 µA max. Icc) power-down mode makes the  
PEEL™22LV10AZ ideal for a broad range of battery-powered  
portable equipment applications, from hand-held meters to PCM-  
CIA modems. EE-reprogrammability provides both the conve-  
nience of fast reprogramming for product development and quick  
product personalization in manufacturing, including Engineering  
Change Orders.  
The differences between the PEEL™22LV10AZ and  
PEEL™22CV10A include the addition of programmable clock  
polarity, p-term clock, and Schmitt trigger input buffers on all  
inputs, including the clock. Schmitt trigger inputs allow direct  
input of slow signals such as biomedical and sine waves or  
clocks. Like the PEEL™22CV10, the PEEL™22LV10AZ is a pin  
and JEDEC compatible, logical superset of the industry stan- dard  
PAL22V10 SPLD (Figure 26). The PEEL™22LV10AZ pro- vides  
additional architectural features that allow more logic to be  
incorporated into the design. The PEEL™22LV10AZ architec-  
ture allows it to replace over twenty standard 24-pin DIP, SOIC,  
TSSOP and PLCC packages.  
Figure 26 Block Diagram  
Figure 26 Pin Configuration  
I/CLK  
1
24  
VCC  
I
I
2
23  
22  
I/O  
I/O  
3
I
I
4
5
21  
20  
I/O  
I/O  
I/O  
I/O  
™
19  
I
I
6
7
18  
17  
16  
15  
I
I
I
8
I/O  
I/O  
I/O  
9
10  
I
11  
12  
14  
13  
I/O  
I
GND  
TSSOP  
DIP  
PLCC  
SOIC  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent  
accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/10  
1234567...10

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