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PEEL22CV10AP-25L

更新时间： 2024-11-20 20:28:03
品牌 Logo 应用领域
ICT 光电二极管
页数 文件大小 规格书
10页 338K
描述
EE PLD, 25ns, CMOS, PDIP24, 0.300 INCH, LEAD FREE, PLASTIC, DIP-24

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PEEL22CV10AP-25L 技术参数

生命周期：Transferred零件包装代码：DIP
包装说明：DIP,针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.15其他特性：10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
最大时钟频率：33.3 MHzJESD-30 代码：R-PDIP-T24
长度：31.75 mm专用输入次数：11
I/O 线路数量：10端子数量：24
最高工作温度：70 °C最低工作温度：
组织：11 DEDICATED INPUTS, 10 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
可编程逻辑类型：EE PLD传播延迟：25 ns
认证状态：Not Qualified最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

PEEL22CV10AP-25L 数据手册

 浏览型号PEEL22CV10AP-25L的Datasheet PDF文件第2页浏览型号PEEL22CV10AP-25L的Datasheet PDF文件第3页浏览型号PEEL22CV10AP-25L的Datasheet PDF文件第4页浏览型号PEEL22CV10AP-25L的Datasheet PDF文件第5页浏览型号PEEL22CV10AP-25L的Datasheet PDF文件第6页浏览型号PEEL22CV10AP-25L的Datasheet PDF文件第7页 
PEEL™ 22CV10A-7/-10/-15/-25  
CMOS Programmable Electrically Erasable Logic Device  
Features  
High Speed/Low Power  
Architectural Flexibility  
- Speeds ranging from 7ns to 25ns  
- 132 product term X 44 input AND array  
- Up to 22 inputs and 10 outputs  
- Power as low as 30mA at 25MHz  
- Up to 12 configurations per macrocell  
- Synchronous preset, asynchronous clear  
- Independent output enables  
Electrically Erasable Technology  
- Superior factory testing  
- Reprogrammable in plastic package  
- Reduces retrofit and development costs  
- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC  
Application Versatility  
Development/Programmer Support  
- Third party software and programmers  
- Anachip PLACE Development Software  
- Replaces random logic  
- Pin and JEDEC compatible with 22V10  
- Enhanced Architecture fits more logic  
than ordinary PLDs  
General Description  
The PEEL™22CV10A is a Programmable Electrically Eras-  
able Logic (PEEL™) device providing an attractive alterna-  
tive to ordinary PLDs. The PEEL™22CV10A offers the  
performance, flexibility, ease of design and production  
practicality needed by logic designers today. The  
PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP  
and 28-pin PLCC packages (see Figure 1), with speeds  
ranging from 7ns to 25ns and with power consumption as low  
as 30mA. EE-reprogrammability provides the conve- nience  
of instant reprogramming for development and a reusable  
also improves factory testability, thus ensuring the highest  
quality possible. The PEEL™22CV10A is JEDEC file com-  
patible with standard 22V10 PLDs. Eight additional configu-  
rations per macrocell (a total of 12) are also available by  
using the “+” software/programming option (i.e., 22CV10A+  
& 22CV10A++). The additional macrocell configurations  
allow more logic to be put into every design. Programming  
and development support for the PEEL™22CV10A are pro-  
vided by popular third-party programmers and develop-  
ment software. Anachip also offers free PLACE  
development software.  
production  
inventory,  
minimizing  
the  
impact  
of  
programming changes or errors. EE-reprogrammability  
Figure 1. Pin Configuration  
Figure 2. Block Diagram  
I/CLK  
1
24  
VCC  
I
I
2
3
23  
22  
I/O  
I/O  
I
I
4
5
21  
20  
I/O  
I/O  
I
I
6
7
19  
18  
I/O  
I/O  
I
I
I
8
17  
16  
15  
I/O  
I/O  
I/O  
9
10  
I
11  
12  
14  
13  
I/O  
I
GND  
TSSOP  
DIP  
SOIC  
PLCC  
*Optional extra ground pin for  
-7/I-7 speed grade.  
9
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under  
any patent accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/10  
1234567...10

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