Datasheet > PEEL20V8P-25

PEEL20V8P-25

更新时间： 2024-11-20 19:42:07

品牌	Logo	应用领域
ICT		时钟输入元件光电二极管可编程逻辑
页数	文件大小	规格书
10页	198K
描述
EE PLD, 25ns, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24

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中文翻译

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技术参数
数据手册

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PEEL20V8P-25 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	24
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	最大时钟频率：	37 MHz
JESD-30 代码：	R-PDIP-T24	长度：	31.75 mm
专用输入次数：	12	I/O 线路数量：	8
端子数量：	24	最高工作温度：	70 °C
最低工作温度：		组织：	12 DEDICATED INPUTS, 8 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	可编程逻辑类型：	EE PLD
传播延迟：	25 ns	认证状态：	Not Qualified
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	7.62 mm
Base Number Matches：	1

PEEL20V8P-25 数据手册

Preliminary

Commercial

PEEL 20V8 -15/-25

CMOS Programmable Electrically Erasable Logic Device

Features

■ Compatible with Popular 20V8 Devices

20V8 socket and function compatible

■ Icc

20mA typical Icc

Programs with standard 20V8 JEDEC file

24-pin DIP/SOIC, 28-pin PLCC packages

■ Development/Programmer Support

Third party software and programmers

ICT PLACE Development Software and

PDS-3 programmer

■ CMOS Electrically Erasable Technology

Superior factory testing

Automatic programmer translation and

JEDEC file translation software available

for the most popular PAL devices

Reprogrammable in plastic package

Reduces retrofit and development costs

■ Application Versatility

Replaces random logic

Super-sets standard 24-pin PLDs (PALs)

General Description

The PEEL20V8 is a Programmable Electrically

Erasable Logic (PEEL) device providing an attrac-

tive alternative to ordinary PLDs. The PEEL20V8

offers the performance, flexibility, ease-of-design

and production practicality needed by logic design-

ers today. The PEEL20V8 is available in 24-pin DIP

and PLCC packages (see Figure 1) with speeds

ranging from 15ns to 25ns and power consumption

as low as 20mA. EE-reprogrammability provides the

convenience of instant reprogramming for develop-

ment and a reusable production inventory minimiz-

ing the impact of programming changes or errors.

EE-reprogrammability also improves factory test-

ability, thus ensuring the highest quality possible.

The PEEL20V8 is socket and function compatible

with other 20V8 devices. Its architecture allows it to

replace many standard 24-pin PALs. See Figure 2.

ICT’s PEEL20V8 can be programmed with any ex-

isting 20V8 JEDEC file. Some programmers also

allow the PEEL20V8 to be programmed directly

from PAL 20L8, 20R4, 20R6 and 20R8 JEDEC files.

Additional development and programming support for

the PEEL20V8 is provided by popular third-party pro-

grammers and development software. ICT also offers

free PLACE development software and a low-cost

development system (PDS-3).

Pin Configuration (Figure 1)

Block Diagram (Figure 2)

I/ CLK

CLK

PEEL

"AND"

ARRAY

I/ O

MACRO

CELL

64 TERMS

40 INPUTS

DIP

I/ OE

PLCC

3 - 25

12 3 4 5 6 7...10

中文翻译

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与PEEL20V8P-25相关器件

型号	品牌	获取价格	描述	数据表
PEEL20V8PL-10	ETC	获取价格	Electrically-Erasable PLD
PEEL20V8PL-15	ICT	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
PEEL20V8PL-25	ETC	获取价格	Electrically-Erasable PLD
PEEL20V8PL-7	ICT	获取价格	EE PLD, 7.5ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
PEEL20V8PQ-15	ICT	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
PEEL20V8PQ-25	ICT	获取价格	EE PLD, 25ns, PAL-Type, CMOS, PDIP24, 0.300 INCH, PLASTIC, DIP-24
PEEL20V8SL-10	ICT	获取价格	EE PLD, 10ns, PAL-Type, CMOS, PDSO24, SOIC-24
PEEL20V8SL-15	ICT	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PDSO24, SOIC-24
PEEL20V8SL-25	ICT	获取价格	EE PLD, 25ns, PAL-Type, CMOS, PDSO24, SOIC-24
PEEL20V8SL-7	ICT	获取价格	EE PLD, 7.5ns, PAL-Type, CMOS, PDSO24, SOIC-24

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