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PEEL18LV8ZTI-15L

更新时间： 2024-11-18 21:55:27
品牌 Logo 应用领域
易亨 - ANACHIP 可编程逻辑光电二极管时钟
页数 文件大小 规格书
10页 231K
描述
CMOS Programmable Electrically Erasable Logic Device

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中文翻译

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PEEL18LV8ZTI-15L 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：TSSOP, TSSOP20,.25Reach Compliance Code：unknown
风险等级：5.79Is Samacsys：N
架构：PAL-TYPE最大时钟频率：41.67 MHz
JESD-30 代码：R-PDSO-G20输入次数：18
输出次数：8产品条款数：113
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：3/3.3 V
可编程逻辑类型：EE PLD传播延迟：20 ns
认证状态：Not Qualified子类别：Programmable Logic Devices
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
Base Number Matches：1

PEEL18LV8ZTI-15L 数据手册

 浏览型号PEEL18LV8ZTI-15L的Datasheet PDF文件第2页浏览型号PEEL18LV8ZTI-15L的Datasheet PDF文件第3页浏览型号PEEL18LV8ZTI-15L的Datasheet PDF文件第4页浏览型号PEEL18LV8ZTI-15L的Datasheet PDF文件第5页浏览型号PEEL18LV8ZTI-15L的Datasheet PDF文件第6页浏览型号PEEL18LV8ZTI-15L的Datasheet PDF文件第7页 
PEEL™ 18LV8Z-15 / I-15  
CMOS Programmable Electrically Erasable Logic Device  
Features  
•
Low Voltage, Ultra Low Power Operation  
•
Architectural Flexibility  
- Vcc = 2.7 to 3.6 V  
- Enhanced architecture fits in more logic  
- 113 product terms x 36 input AND array  
- 10 inputs and 8 I/O pins  
- Icc = 5 µA (typical) at standby  
- Icc = 1.5 mA (typical) at 1 MHz  
- Meets JEDEC LV Interface Spec (JEDSD8-A)  
- 5 Volts tolerant inputs and I/O’s  
- 12 possible macrocell configurations  
- Asynchronous clear, Synchronous preset  
- Independent output enables  
•
•
CMOS Electrically Erasable Technology  
- Superior factory testing  
- Programmable clock; pin 1 or p-term  
- Programmable clock polarity  
- Reprogrammable in plastic package  
- Reduces retrofit and development costs  
- 20 Pin DIP/SOIC/TSSOP and PLCC  
- Schmitt triggers on clock and data inputs  
Application Versatility  
•
Schmitt Trigger Inputs  
- Replaces random logic  
- Eliminates external Schmitt trigger devices  
- Ideal for encoder designs  
- Super set of standard PLDs  
- Pin and JEDEC compatible with 16V8  
- Ideal for battery powered systems  
- Replaces expensive oscillators  
General Description  
The PEEL18LV8Z is a Programmable Electrically Erasable The differences between the PEEL18LV8Z and  
Logic (PEEL) SPLD (Simple Programmable Logic Device) PEEL18CV8 include the addition of programmable clock  
that operates over the supply voltage range of 2.7V-3.6V polarity, p-term clock, and Schmitt trigger input buffers on  
and features ultra-low, automatic "zero" power-down all inputs, including the clock. Schmitt trigger inputs allow  
operation. The PEEL18LV8Z is logically and functionally direct input of slow or noisy signals.  
similar to Anachip's 5V PEEL18CV8 and PEEL18CV8Z.  
Like the PEEL18CV8, the PEEL18LV8Z is a logical  
The "zero power" (25 µA max. Icc) power-down mode  
superset of the industry standard PAL16V8 SPLD. The  
makes the PEEL18LV8Z ideal for a broad range of battery-  
PEEL18LV8Z provides additional architectural features that  
powered portable equipment applications, from hand-held  
allow more logic to be incorporated into the design.  
meters to PCMCIA modems. EE-reprogrammability  
Anachip's JEDEC file translator allows easy conversion of  
provides both the convenience of fast reprogramming for  
existing 20 pin PLD designs to the PEEL18LV8Z  
product development and quick product personalization in  
architecture without the need for redesign. The  
manufacturing, including Engineering Change Orders.  
PEEL18LV8Z architecture allows it to replace over twenty  
standard 20-pin DIP, SOIC, TSSOP and PLCC packages.  
I/CLK1  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
I/CLK1  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
CLK MUX (Optional)  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ª
9
10  
9
10  
GND  
GND  
I
DIP  
TSSOP  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
I/CLK1  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
I
I
I
I
I
I
I
I
3
2
1
19  
20  
I
I
I
I
I
I/O  
I/O  
I/O  
I/O  
I/O  
4
5
6
7
8
18  
17  
16  
15  
14  
9
10 11 12 13  
10  
GND  
PLCC-J  
SOIC  
Figure 2 - Block Diagram  
Figure 1 - Pin Configuration  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights  
under any patent accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/10  
1234567...10

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