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PEEL18LV8ZSI-25

更新时间： 2024-11-19 07:03:35
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CMOS Programmable Electrically Erasable Logic Device

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PEEL18LV8ZSI-25 数据手册

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PEEL™ 18LV8Z-25 / I-35  
CMOS Programmable Electrically Erasable Logic Device  
Features  
•
Low Voltage, Ultra Low Power Operation  
•
Architectural Flexibility  
- Vcc = 2.7 to 3.6 V  
- Enhanced architecture fits in more logic  
- 113 product terms x 36 input AND array  
- 10 inputs and 8 I/O pins  
- Icc = 5 µA (typical) at standby  
- Icc = 1.5 mA (typical) at 1 MHz  
- Meets JEDEC LV Interface Spec (JEDSD8-A)  
- 5 Volts tolerant inputs and I/O’s  
- 12 possible macrocell configurations  
- Asynchronous clear, Synchronous preset  
- Independent output enables  
•
•
CMOS Electrically Erasable Technology  
- Superior factory testing  
- Programmable clock; pin 1 or p-term  
- Programmable clock polarity  
- Reprogrammable in plastic package  
- Reduces retrofit and development costs  
- 20 Pin DIP/SOIC/TSSOP and PLCC  
- Schmitt triggers on clock and data inputs  
Application Versatility  
•
Schmitt Trigger Inputs  
- Replaces random logic  
- Eliminates external Schmitt trigger devices  
- Ideal for encoder designs  
- Super set of standard PLDs  
- Pin and JEDEC compatible with 16V8  
- Ideal for battery powered systems  
- Replaces expensive oscillators  
General Description  
The PEEL18LV8Z is a Programmable Electrically Erasable The differences between the PEEL18LV8Z and  
Logic (PEEL) SPLD (Simple Programmable Logic Device) PEEL18CV8 include the addition of programmable clock  
that operates over the supply voltage range of 2.7V-3.6V polarity, p-term clock, and Schmitt trigger input buffers on  
and features ultra-low, automatic "zero" power-down all inputs, including the clock. Schmitt trigger inputs allow  
operation. The PEEL18LV8Z is logically and functionally direct input of slow or noisy signals.  
similar to Anachip's 5V PEEL18CV8 and PEEL18CV8Z.  
Like the PEEL18CV8, the PEEL18LV8Z is a logical  
The "zero power" (25 µA max. Icc) power-down mode  
superset of the industry standard PAL16V8 SPLD. The  
makes the PEEL18LV8Z ideal for a broad range of battery-  
PEEL18LV8Z provides additional architectural features that  
powered portable equipment applications, from hand-held  
allow more logic to be incorporated into the design.  
meters to PCMCIA modems. EE-reprogrammability  
Anachip's JEDEC file translator allows easy conversion of  
provides both the convenience of fast reprogramming for  
existing 20 pin PLD designs to the PEEL18LV8Z  
product development and quick product personalization in  
architecture without the need for redesign. The  
manufacturing, including Engineering Change Orders.  
PEEL18LV8Z architecture allows it to replace over twenty  
standard 20-pin DIP, SOIC, TSSOP and PLCC packages.  
I/CLK1  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
I/CLK1  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
CLK MUX (Optional)  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ª
9
10  
9
10  
GND  
GND  
I
DIP  
TSSOP  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
I/CLK1  
VCC  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
I
I
I
I
I
I
I
I
3
2
1
19  
20  
I
I
I
I
I
I/O  
I/O  
I/O  
I/O  
I/O  
4
5
6
7
8
18  
17  
16  
15  
14  
9
10 11 12 13  
10  
GND  
PLCC-J  
SOIC  
Figure 2 - Block Diagram  
Figure 1 - Pin Configuration  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights  
under any patent accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/10  
1234567...10

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