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PEEL18CV8PI-25 PDF预览

PEEL18CV8PI-25

更新时间: 2024-11-28 20:34:55
品牌 Logo 应用领域
美台 - DIODES 时钟输入元件光电二极管可编程逻辑
页数 文件大小 规格书
9页 648K
描述
EE PLD, 25ns, PAL-Type, CMOS, PDIP20, 0.300 INCH, PLASTIC, DIP-20

PEEL18CV8PI-25 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:0.300 INCH, PLASTIC, DIP-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.41
Is Samacsys:N架构:PAL-TYPE
最大时钟频率:28.5 MHzJESD-30 代码:R-PDIP-T20
JESD-609代码:e0长度:26.162 mm
专用输入次数:9I/O 线路数量:8
输入次数:18输出次数:8
产品条款数:74端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
组织:9 DEDICATED INPUTS, 8 I/O输出函数:MACROCELL
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):235
电源:5 V可编程逻辑类型:EE PLD
传播延迟:25 ns认证状态:Not Qualified
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:10
宽度:7.62 mmBase Number Matches:1

PEEL18CV8PI-25 数据手册

 浏览型号PEEL18CV8PI-25的Datasheet PDF文件第2页浏览型号PEEL18CV8PI-25的Datasheet PDF文件第3页浏览型号PEEL18CV8PI-25的Datasheet PDF文件第4页浏览型号PEEL18CV8PI-25的Datasheet PDF文件第5页浏览型号PEEL18CV8PI-25的Datasheet PDF文件第6页浏览型号PEEL18CV8PI-25的Datasheet PDF文件第7页 
Not recommended for New designs -  
contact factory for availability  
PEEL™ 18CV8 -7/-10/-15/-25  
CMOS Programmable Electrically Erasable Logic Device  
Features  
Architectural Flexibility  
Multiple Speed Power, Temperature Options  
- Enhanced architecture fits in more logic  
- 74 product terms x 36 input AND array  
- 10 inputs and 8 I/O pins  
- VCC = 5 Volts ±10%  
- Speeds ranging from 7ns to 25 ns  
- Power as low as 37mA at 25MHz  
- Commercial and industrial versions available  
- 12 possible macrocell configurations  
- Asynchronous clear  
CMOS Electrically Erasable Technology  
- Independent output enables  
- Superior factory testing  
- 20 Pin DIP/SOIC/TSSOP and PLCC  
- Reprogrammable in plastic package  
- Reduces retrofit and development costs  
Application Versatility  
Development / Programmer Support  
- Third party software and programmers  
- WinPLACE Development Software  
- PLD-to-PEEL™ JEDEC file translator  
- Replaces random logic  
- Super sets PLDs (PAL, GAL, EPLD)  
- Enhanced Architecture fits more logic than ordinary PLDs  
General Description  
The PEEL™18CV8 is a Programmable Electrically Erasable  
Logic (PEEL™) device providing an attractive alternative to  
ordinary PLDs. The PEEL™18CV8 offers the performance, flex-  
ibility, ease of design and production practicality needed by logic  
designers today.  
The PEEL™18CV8 architecture allows it to replace over 20 stan-  
dard 20-pin PLDs (PAL, GAL, EPLD etc.). It also provides addi-  
tional architecture features so more logic can be put into every  
design. Anachip’s JEDEC file translator instantly converts to the  
PEEL™18CV8 existing 20-pin PLDs without the need to rework  
the existing design. Development and programming support for the  
PEEL™18CV8 is provided by popular third-party program- mers  
and development software.  
The PEEL™18CV8 is available in 20-pin DIP, PLCC, SOIC and  
TSSOP packages with speeds ranging from 7ns to 25ns with  
power consumption as low as 37mA. EE-Reprogrammability  
provides the convenience of instant reprogramming for develop-  
ment and reusable production inventory minimizing the impact of  
programming changes or errors. EE-Reprogrammability also  
improves factory testability, thus assuring the highest quality pos-  
sible.  
Figure 3 Block Diagram  
Figure 2 Pin Configuration  
I/CLK  
1
20  
VCC  
I
I
2
3
19  
18  
17  
16  
I/O  
I/O  
I/O  
I/O  
I
I
4
5
I
I
6
7
15  
14  
I/O  
I/O  
I
I
8
9
13  
12  
11  
I/O  
I/O  
I
GND  
10  
TSSOP  
DIP  
SOIC  
PLCC  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent  
accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/9  

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