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PDU54-3000M PDF预览

PDU54-3000M

更新时间： 2024-02-04 07:05:11
品牌 Logo 应用领域
DATADELAY 延迟线逻辑集成电路光电二极管
页数 文件大小 规格书
4页 250K
描述
4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU54)

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中文翻译

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PDU54-3000M 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：DIP
包装说明：DIP,针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.14Is Samacsys：N
JESD-30 代码：R-XDIP-T24JESD-609代码：e3
长度：32.258 mm逻辑集成电路类型：ACTIVE DELAY LINE
功能数量：1抽头/阶步数：15
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出特性：OPEN-EMITTER
输出极性：TRUE封装主体材料：UNSPECIFIED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
可编程延迟线：YES认证状态：Not Qualified
座面最大高度：10.033 mm表面贴装：NO
技术：ECL温度等级：MILITARY
端子面层：Tin (Sn)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED总延迟标称（td）：45 ns
宽度：15.24 mmBase Number Matches：1

PDU54-3000M 数据手册

 浏览型号PDU54-3000M的Datasheet PDF文件第2页浏览型号PDU54-3000M的Datasheet PDF文件第3页浏览型号PDU54-3000M的Datasheet PDF文件第4页 
PDU54  
4-BIT, ECL-INTERFACED  
PROGRAMMABLE DELAY LINE  
(SERIES PDU54)  
FEATURES  
PACKAGES  
N/C  
N/C  
GND  
N/C  
N/C  
N/C  
N/C  
N/C  
GND  
OUT  
N/C  
N/C  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
IN  
N/C  
N/C  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
IN  
1
2
3
4
5
6
7
8
2
N/C  
VEE  
A3  
N/C  
VEE  
A3  
N/C  
N/C  
A2  
A1  
VEE  
A0  
•
•
•
•
•
Digitally programmable in 16 delay steps  
Monotonic delay-versus-address variation  
Precise and stable delays  
Input & outputs fully 100K-ECL interfaced & buffered  
Available in 24-pin DIP (600 mil) socket or SMD  
3
GND  
N/C  
N/C  
N/C  
N/C  
N/C  
GND  
OUT  
N/C  
N/C  
4
5
N/C  
N/C  
A2  
6
7
8
A1  
9
VEE  
A0  
10  
11  
12  
9
N/C  
N/C  
10  
11  
12  
N/C  
N/C  
PDU54-xx DIP  
PDU54-xxC4 SMD  
PDU54-xxM Military DIP  
PDU54-xxMC4 Mil SMD  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The PDU54-series device is a 4-bit digitally programmable delay line. The  
delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the  
address code (A3-A0) according to the following formula:  
IN  
Signal Input  
OUT Signal Output  
A3-A0 Address Bits  
VEE -5 Volts  
TDA = TD0 + TINC * A  
GND Ground  
where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of  
the device. The incremental delay is specified by the dash number of the device and can range from  
100ps through 3000ps, inclusively. The address is not latched and must remain asserted during normal  
operation.  
SERIES SPECIFICATIONS  
DASH NUMBER SPECIFICATIONS  
•
Total programmed delay tolerance: 5% or 40ps,  
Part  
Incremental Delay  
Per Step (ps)  
100 ± 50  
Total Delay  
Change (ns)  
1.50  
whichever is greater  
Number  
PDU54-100  
PDU54-200  
PDU54-250  
PDU54-400  
PDU54-500  
PDU54-750  
PDU54-1000  
PDU54-1200  
PDU54-1500  
PDU54-2000  
PDU54-2500  
PDU54-3000  
•
•
•
•
•
•
•
Inherent delay (TD0): 3.3ns typical  
Address to input setup (TAIS): 2.9ns  
Operating temperature: 0° to 85° C  
Temperature coefficient: 100PPM/°C (excludes TD0)  
Supply voltage VEE: -5VDC ± 0.7V  
Power Supply Current: -300ma typical (50Ω to -2V)  
Minimum pulse width: 3ns or 10% of total delay,  
whichever is greater  
3.00  
200 ± 60  
3.75  
250 ± 60  
6.00  
400 ± 80  
7.50  
500 ± 100  
750 ± 100  
11.25  
15.00  
1000 ± 200  
1200 ± 200  
1500 ± 200  
2000 ± 400  
2500 ± 400  
3000 ± 500  
18.00  
22.50  
30.00  
•
Minimum period: 8ns or 2 x pulse width, whichever  
is greater  
37.50  
45.00  
A3-A0  
A i-1  
Ai  
NOTE: Any dash number between 100 and 3000  
not shown is also available.  
PWIN  
TOAX  
TAIS  
IN  
TDA  
PWOUT  
OUT  
Figure 1: Timing Diagram  
1997 Data Delay Devices  
Doc #98004  
3/18/98  
DATA DELAY DEVICES, INC.  
1
3 Mt. Prospect Ave. Clifton, NJ 07013  
1234

中文翻译

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