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PDSP16488AMAGCPR PDF预览

PDSP16488AMAGCPR

更新时间： 2024-09-29 03:39:11
品牌 Logo 应用领域
加拿大卓联 - ZARLINK DSP外围设备微控制器和处理器外围集成电路时钟
页数 文件大小 规格书
30页 293K
描述
Single Chip 2D Convolver with Integral Line Delays

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中文翻译

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PDSP16488AMAGCPR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QFF, QFL132,.95SQ,25Reach Compliance Code：compliant
ECCN代码：3A001.A.2.CHTS代码：8542.39.00.01
风险等级：5.25Is Samacsys：N
边界扫描：NO最大时钟频率：40 MHz
外部数据总线宽度：16JESD-30 代码：S-CQFP-F132
JESD-609代码：e0长度：24.1935 mm
低功率模式：NO端子数量：132
最高工作温度：125 °C最低工作温度：-55 °C
输出数据总线宽度：16封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QFF封装等效代码：QFL132,.95SQ,25
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：225电源：5 V
认证状态：Not Qualified筛选级别：MIL-STD-883
座面最大高度：3.33 mm子类别：DSP Peripherals
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：0.635 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：24.1935 mm
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, CONVOLVERBase Number Matches：1

PDSP16488AMAGCPR 数据手册

 浏览型号PDSP16488AMAGCPR的Datasheet PDF文件第2页浏览型号PDSP16488AMAGCPR的Datasheet PDF文件第3页浏览型号PDSP16488AMAGCPR的Datasheet PDF文件第4页浏览型号PDSP16488AMAGCPR的Datasheet PDF文件第5页浏览型号PDSP16488AMAGCPR的Datasheet PDF文件第6页浏览型号PDSP16488AMAGCPR的Datasheet PDF文件第7页 
PDSP16488A MA  
Single Chip 2D Convolver with Integral Line Delays  
Supersedes January 1997 version, DS3742 - 3.1  
DS3742 - 5.0 November 2000  
The PDSP16488A is a fully integrated, application spe-  
cific, image processing device. It performs a two dimensional  
convolution between the pixels within a video window and a  
set of stored coefficients. An internal multiplier accumulator  
array can be multi-cycled at double or quadruple the pixel  
clock rate. This then gives the window size options listed in  
Table 1.  
An internal 32k bit RAM can be configured to provide  
either four or eight line delays. The length of each delay can  
be programmed to the users requirement, up to a maximum of  
1024 pixels per line. The line delays are arranged in two  
groups,whichmaybeinternallyconnectedinseriesormay be  
configured to accept separate pixel inputs. This allows inter-  
laced video or frame to frame operations to be supported.  
The 8 bit coefficients are also stored internally and can  
be downloaded from a host computer or from an EPROM. No  
additionallogicisrequiredtosupporttheEPROMandasingle  
device can support up to 16 convolvers.  
FEATURES  
I
The PDSP16488A is a fully compatible replacement  
for the PDSP16488  
I
I
I
I
I
I
I
I
8 or 16 bit pixels with rates up to 40 MHz  
Window sizes up to 8 x 8 with a single device  
Eight internal line delays  
Supports interlace and frame to frame operations  
Coefficients supplied from an EPROM or remote host  
Expandable in both X and Y for larger windows  
Gain control and pixel output manipulation  
132 pin QFP  
Rev  
A
B
C
D
Date  
MAR 1993 JUL 1996 JAN1997  
NOTE  
The PDSP16488A contains an expansion adder and  
delay network which allows several devices to be cascaded.  
Convolvers with larger windows can then be fabricated as  
shown in Table 2.  
Polyimide is used as an inter-layer dielectric and as  
glassivation.  
Polymeric material is also used for die attach which according  
to the requirement in paragraph 1.2.1.b. (2) precludes  
catagorising this device as fully compliant. In every other  
respectthisdevicehasbeenmanufacturedandscreenedinfull  
accordance with the requirements of Mil-Std 883 (latest revi-  
sion).  
Intermediate 32 bit precision is provided to avoid any  
dangerofoverflow, but thefinalresultwillnotnormallyoccupy  
all bits. The PDSP16488A thus provides a multiplier in the  
output path, which allows the user to align the result to the  
most significant end of the 32 bit word.  
CHANGE NOTIFICATION  
The change notification requirements of MIL-PRF-38535 will  
be implemented on this device type. Known customers will be  
notifiedofanychangessincethelastbuywhenorderingfurther  
parts if significant changes have been made.  
Data  
Size  
Window Size  
Width X Depth  
Max Pixel Line  
Rate  
Delays  
8
8
8
16  
16  
4
8
8
4
8
4
4
8
4
4
40MHz 4x1024  
20MHz 4x1024  
10MHz 8x512  
20MHz 4x512  
10MHz 4x512  
PIXEL  
CLOCK  
GENERATOR  
EPROM  
POWER ON  
RESET  
ADDR DATA  
Table 1 Single Device Configurations  
CLK  
SYNC  
RES  
DELAYED  
SYNC  
SYNC  
EXTRACT  
Pixel  
Window size  
Max Pixel  
Rate  
BYPASS  
Size 3x3 5x5  
7x7 9x9 11x11 15x15 23x23  
PDSP  
8
16  
8
1
1
1
1
1
2
1
2
2
4
4
-
1
4
-
4
-
4
-
9
-
10MHz  
10MHz  
20MHz  
20MHz  
40MHz  
40MHz  
16488A  
DATA  
IN  
A/D  
CONVERTER  
OUTPUT  
DATA  
2
CONVOLVER  
2
6
-
6
-
8
-
-
16  
8
4
-
OPTIONAL  
FIELD  
STORE  
AUX  
DATA  
*
4 *  
-
-
-
-
-
COMPOSITE  
16  
-
-
-
-
* Maximum rate is limited to 30 MHz by line store expansion delays  
Fig. 1 Typical , Stand Alone, Real Time System  
Table 2 Devices needed to implement typical window sizes  
1234567...30

中文翻译

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