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PDSP16488A

更新时间: 2024-09-26 03:42:47
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
33页 462K
描述
Single Chip 2D Convolver with Integral Line Delays

PDSP16488A 数据手册

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PDSP16488A  
Single Chip 2D Convolver with Integral Line Delays  
Advance Information  
DS3713  
ISSUE 6.4  
December 1997  
The PDSP16488A is a fully integrated, application specific,  
image processing device. It performs a two dimensional convo-  
lution between the pixels within a video window and a set of  
stored coefficients. An internal multiplier accumulator array can  
be multi-cycled at double or quadruple the pixel clock rate. This  
then gives the window size options listed in Table 1.  
An internal 32kbit RAM can be configured to provide either  
four or eight line delays. The length of each delay can be  
programmedtotheusersrequirement, uptoamaximumof1024  
pixels per line. The line delays are arranged in two groups,which  
may be internally connected in series or may be configured to  
accept separate pixel inputs. This allows interlaced video or  
frame to frame operations to be supported.  
POWER  
ON  
EPROM  
ADDR DATA  
COMPOSITE  
DATA  
PIXEL  
CLOCK  
GEN  
RESET  
CLK  
RES  
DELOP  
SYNC  
DELAYED  
SYNC  
HRES  
BYPASS  
SYNC  
EXTRACT  
ODD FIELD  
PDSP16488A  
OUTPUT  
DATA  
ADC  
L7:0  
D15:0  
OPTIONAL  
FIELD  
DELAY  
The 8-bit coefficients are also stored internally and can be  
downloaded from a host computer or from an EPROM. No  
additional logic is required to support the EPROM and a single  
device can support up to 16 convolvers.  
IP7:0  
The PDSP16488A contains an expansion adder and delay  
network which allows several devices to be cascaded. Con-  
volvers with larger windows can then be fabricated as shown in  
Table 2.  
Intermediate 32-bit precision is provided to avoid any danger  
of overflow, but the final result will not normally occupy all bits.  
The PDSP16488A thus provides a gain control block in the  
output path, which allows the user to align the result to the most  
significant end of the 32-bit word.  
Fig. 1 Typical stand-alone real time system  
FEATURES  
The PDSP16488A is a replacement for the  
PDSP16488 (see Note below)  
8 or 16-bit Pixels with rates up to 40 MHz  
Window Sizes up to 838 with a Single Device  
Eight Internal Line Delays  
Supports Interlace and Frame-to-Frame Operations  
Coefficients Supplied from an EPROM or Remote Host  
Expandable in both X and Y for Larger Windows  
Gain Control and Pixel Output Manipulation  
84-pin PGA or 132-pin QFP Package Options  
Window size  
Pixel  
size  
Maximum pixel  
rate (MHz)  
Line delays  
Width  
Depth  
8
8
8
16  
16  
4
8
8
4
8
4
4
8
4
4
20  
20  
10  
20  
10  
431024  
431024  
83512  
43512  
43512  
Note: PDSP16488Adevicesarenotguaranteedtocascadewith  
PDSP16488devices. ZarlinkSemiconductordonotrecommend  
thatPDSP16488AbemixedwithPDSP16488devicesinasingle  
equipment design. The PDSP16488A requires external pullup  
resistorsinEPROMMode(see StaticElectricalCharacteristics).  
Table 1 Single PDSP16488A configurations  
Max.  
No. of PDSP16488As for N3N window size  
ORDERING INFORMATION  
Commercial (0°C to 170°C)  
PDSP16488A / C0 / AC (PGA)  
Industrial (240°C to 185°C)  
PDSP16488A / B0 / AC (PGA)  
PDSP16488A / B0 / GC (QFP)  
Military (255°C to 1125°C)  
PDSP16488A / A0 / AC (PGA)  
PDSP16488A / A0 / GC (QFP)  
PDSP16488A / MA / ACBR (PGA) MIL-STD-883 Class B*  
PDSP16488A / MA / GCPR (QFP) MIL-STD-883 Class B*  
*See Notes following Static Electrical CharacteristicsTable  
pixel Pixel  
rate size  
(MHz)  
333 535 737 939 11311 15315 23323  
10  
10  
20  
20  
40  
40  
8
16  
8
16  
8
16  
1
1
1
1
1
2
1
2
2
4
4*  
-
1
2
2
4
4*  
-
4
-
6
-
-
-
4
-
6
-
-
-
4
-
8
-
-
-
9
-
-
-
-
-
*Maximum rate is limited to 30MHz by line store expansion delays  
Table 2 PDSP16488As needed to implement typical window sizes  

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