PDSP16330/A/B
Pythagoras Processor
Supersedes version September 1996, DS3884 - 1.3
DS3884 - 2.1 November 1998
The PDSP16330 is a high speed digital CMOS IC that
converts Cartesian data (Real and Imaginary) into Polar form
(Magnitude and Phase), at rates up to 20MHz. Cartesian
16+16 bit 2's complement or Sign-Magnitude data is
convertedinto16bitPhaseformat.TheMagnitudeoutputmay
be scaled in amplitude by powers of 2. The Phase output
represents a full 2 x π field to eliminate phase ambiguities.
PIN 1A INDEX MARK
ON TOP SURFACE
A
B
C
D
E
F
Polyimide is used as an inter-layer dielectric and as
glassivation.
The PDSP16330 is offered in three speed grades: a
basic 10MHz part (PDSP16330), a 20MHz version
(PDSP16330A) and a 25MHz version (PDSP16330). A MIL-
STD-883 version is also detailed in a separate datasheet.
G
H
J
K
L
FEATURES
11 10
9
8
7
6
5
4
3
2 1
25MHz Cartesian to Polar Conversion
AC84
16-Bit Cartesian Inputs
16-Bit Magnitude Output
Fig.1 Pin connections - bottom view (PGA)
12-Bit Phase Output
2’s Complement or Sign-Magnitude Input Formats
Three-state Outputs and Independent
Data Enables Simplify System Interfacing
Magnitude Scaling Facility with Overflow Flag
Less than 400 mW Power Dissipation at 10MHz
84-pin PGA or 100 pin QFP Package or 84 LCC
GC100
APPLICATIONS
Digital Signal Processing
Digital Radio
Radar Processing
Sonar Processing
Robotics
ORDERING INFORMATION
Fig.2 Pin connections - QFP Package
Commercial (0°C to +70°C)
PDSP16330A CO AC
PDSP16330B CO AC
Industrial (-40°C to +85°C)
PDSP16330A BO AC
PDSP16330A/IG/GC1R
PDSP16330B BO AC
Military (-55°C to +125°C)
PDSP16330A AO AC
PDSP16330/MC/GC1R
(20MHZ - PGA Package)
(25MHZ - PGA Package)
ASSOCIATED PPODUCTS
PDSP16112
PDSP16116
PDSP16318
PDSP16350
16 X 12 Complex Multiplier
16 X 16 Complex Multiplier
Complex Accumulator
I/Q Splitter and NCO
20MHZ - PGA Package
20MHZ - GC Package
25MHZ - PGA Package
PDSP16510A Stand Alone FFT Processor
20MHZ - PGA Package
10MHz - GC Package
Mil 883C Screened