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PDM41532LA15TA PDF预览

PDM41532LA15TA

更新时间: 2024-11-11 10:02:27
品牌 Logo 应用领域
IXYS 静态存储器光电二极管
页数 文件大小 规格书
10页 230K
描述
Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, PLASTIC, TSOP2-44

PDM41532LA15TA 数据手册

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PDM41532  
PRELIMINARY  
64K x 16 CMOS  
Static RAM  
1
2
Description  
Features  
The PDM41532 is a high-performance CMOS static  
RAM organized as 65,536 x 16 bits. The PDM41532  
features low power dissipation using chip enable  
(CE) and has an output enable input (OE) for fast  
memory access. Byte access is supported by upper  
and lower byte controls.  
High-speed access times  
- Com’l: 10, 12, 15 and 20 ns  
- Ind: 12, 15 and 20 ns  
Low power operation (typical)  
- PDM41532SA  
Active: 350 mW  
Standby: 50 mW  
- PDM41532LA  
Active: 300 mW  
3
The PDM41532 operates from a single 5.0V power  
supply and all inputs and outputs are fully TTL-  
compatible. The PDM41532 comes in two versions,  
the standard power version PDM41532SA and a low  
power version PDM41532LA. The two versions are  
functionally the same and only differ in their power  
consumption.  
Standby: 25mW  
High-density 64K x 16 architecture  
Single +5V (±10%) power supply  
Fully static operation  
TTL-compatible inputs and outputs  
Output buffer controls: OE  
Data byte controls: LB, UB  
Packages:  
The PDM41532 is available in a 44-pin 400 mil plas-  
tic SOJ and a 44-pin plastic TSOP (II) package  
suitable for high-density surface assembly and is  
suitable for use in high-speed applications such as  
cache memory and high-speed storage.  
5
6
Plastic SOJ (400 mil) - SO  
Plastic TSOP (II) - T  
7
Functional Block Diagram  
Vcc  
8
Vss  
Memory  
A8-A0  
Cell  
Array  
256 x 128 x 32  
9
Data  
Input/  
Output  
Buffer  
I/O15-I/O0  
Sense Amp  
10  
11  
12  
Column  
Decoder  
WE  
OE  
UB  
LB  
Control  
Logic  
Column  
Address  
Buffer  
Clock  
Generator  
CE  
A15-A9  
Rev. 1.3 - 4/10/98  
1

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