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PDM41256LA8TA PDF预览

PDM41256LA8TA

更新时间: 2024-11-19 15:47:39
品牌 Logo 应用领域
IXYS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 283K
描述
Standard SRAM, 32KX8, 8ns, CMOS, PDSO28, PLASTIC, TSOP1-28

PDM41256LA8TA 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSOP
包装说明:PLASTIC, TSOP1-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.65
Is Samacsys:N最长访问时间:8 ns
JESD-30 代码:R-PDSO-G28长度:11.8 mm
内存密度:262144 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:105 °C最低工作温度:-40 °C
组织:32KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP1封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.55 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

PDM41256LA8TA 数据手册

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PDM41256  
256K Static RAM  
32K x 8-Bit  
1
2
Description  
Features  
The PDM41256 is a high-performance CMOS static  
RAM organized as 32,768 x 8 bits. Writing to this  
device is accomplished when the write enable (WE)  
and the chip enable (CE) inputs are both LOW.  
Reading is accomplished when WE remains HIGH  
and CE and OE are both LOW.  
High-speed access times  
Com’l: 7, 8, 10, 12 and 15ns  
Ind’l: 8, 10, 12 and 15ns  
(use 15ns for slower designs)  
Low power operation (typical)  
- PDM41256SA  
Active: 475 mW  
Standby: 100 mW  
- PDM41256LA  
Active: 425mW  
The PDM41256 operates from a single +5V power  
supply and all the inputs and outputs are fully TTL-  
compatible. The PDM41256 comes in two versions:  
the standard power version PDM41256SA and the  
low power version PDM41256LA. Both versions are  
functionally the same and differ only in their power  
consumption.  
4
Standby: 25 mW  
Single +5V (±10%) power supply  
TTL-compatible inputs and outputs  
Packages  
5
The PDM41256 is available in a 28-pin plastic TSOP  
(I) and a 28-pin 300-mil plastic SOJ.  
Plastic SOJ (300 mil) - SO  
Plastic TSOP (I) - T  
6
Functional Block Diagram  
7
A
0
Decoder  
Memory  
8
Addresses  
Matrix  
A 14  
9
• • • • •  
I/O0  
Input  
Data  
Control  
Column I/O  
10  
11  
12  
I/O7  
CE  
WE  
OE  
Rev. 4.4 - 4/29/98  
1

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