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PCX7457VGU1000LC PDF预览

PCX7457VGU1000LC

更新时间: 2024-11-08 06:09:35
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
64页 667K
描述
RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA483, 29 X 29 MM, 3.22 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-483

PCX7457VGU1000LC 数据手册

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Features  
3000 Dhrystone 2.1 MIPS at 1.3 GHz  
Selectable Bus Clock (30 CPU Bus Dividers up to 28x)  
13 Selectable Core-to-L3 Frequency Divisors  
Selectable MPx/60x Interface Voltage (1.8V, 2.5V)  
Selectable L3 Interface of 1.8V or 2.5V  
PD Typical 12.6W at 1 GHz at VDD = 1.3V; 8.3W at 1 GHz at VDD = 1.1V, Full Operating  
Conditions  
Nap, Doze and Sleep Modes for Power Saving  
Superscalar (Four Instructions Fetched Per Clock Cycle)  
4 GB Direct Addressing Range  
PowerPC®  
7447/7457  
Virtual Memory: 4 Hexabytes (252)  
64-bit Data and 36-bit Address Bus Interface  
Integrated L1: 36 KB Instruction and 32 KB Data Cache  
Integrated L2: 512 KB  
11 Independent Execution Units and Three Register Files  
Write-back and Write-through Operations  
fINT Max = 1 GHz (1.2 GHz to be Confirmed)  
fBUS Max = 133 MHz/166 MHz  
PC7447/57  
Preliminary  
Description  
This document is primarily concerned with the PowerPC PC7457; however, unless  
otherwise noted, all information here also applies to the PC7447. The PC7457 and  
PC7447 are implementations of the PowerPC microprocessor family of reduced  
instruction set computer (RISC) microprocessors. This document describes pertinent  
electrical and physical characteristics of the PC7457.  
The PC7457 is the fourth implementation of the fourth generation (G4) microproces-  
sors from Freescale. The PC7457 implements the full PowerPC 32-bit architecture  
and is targeted at networking and computing systems applications. The PC7457 con-  
sists of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which  
support a glueless backside L3 cache through a dedicated high-bandwidth interface.  
The PC7447 is identical to the PC7457 except it does not support the L3 cache  
interface.  
The core is a high-performance superscalar design supporting a double-precision  
floating-point unit and a SIMD multimedia unit. The memory storage subsystem sup-  
ports the MPX bus interface to main memory and other system resources. The L3  
interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private  
memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes  
may be used as cache; the remaining 2M bytes must be private memory.  
Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455  
application if the core power supply is 1.3V.  
Rev. 5345C–HIREL–07/05  

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