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PCX7457VGU1000LB PDF预览

PCX7457VGU1000LB

更新时间: 2024-11-07 14:44:11
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟ATM异步传输模式外围集成电路
页数 文件大小 规格书
66页 522K
描述
RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA483, 29 X 29 MM, 1.27 MM PITCH, CERAMIC, BGA-483

PCX7457VGU1000LB 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:483
Reach Compliance Code:compliantECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.16
Is Samacsys:N地址总线宽度:36
位大小:32边界扫描:YES
最大时钟频率:167 MHz外部数据总线宽度:64
格式:FLOATING POINT集成缓存:YES
JESD-30 代码:S-CBGA-B483长度:29 mm
低功率模式:YES湿度敏感等级:1
端子数量:483封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
认证状态:Not Qualified座面最大高度:3.2 mm
速度:1000 MHz最大供电电压:1.35 V
最小供电电压:1.25 V标称供电电压:1.3 V
表面贴装:YES技术:CMOS
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:29 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

PCX7457VGU1000LB 数据手册

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Features  
3000 Dhrystone 2.1 MIPS at 1.3 GHz  
Selectable Bus Clock (30 CPU Bus Dividers up to 28x)  
13 Selectable Core-to-L3 Frequency Divisors  
Selectable MPx/60x Interface Voltage (1.8V, 2.5V)  
Selectable L3 Interface of 1.8V or 2.5V  
PD Typical 12.6W at 1 GHz at VDD = 1.3V; 8.3W at 1 GHz at VDD = 1.1V, Full Operating  
Conditions  
Nap, Doze and Sleep Modes for Power Saving  
Superscalar (Four Instructions Fetched Per Clock Cycle)  
4 GB Direct Addressing Range  
PowerPC 7457  
RISC  
Microprocessor  
Virtual Memory: 4 Hexabytes (252)  
64-bit Data and 32-bit Address Bus Interface  
Integrated L1: 32 KB Instruction and 32 KB Data Cache  
Integrated L2: 512 KB  
11 Independent Execution Units and Three Register Files  
Write-back and Write-through Operations  
fINT Max = 1 GHz (1.2 GHz to be Confirmed)  
fBUS Max = 133 MHz/166 MHz  
PC7457/47  
Description  
This document is primarily concerned with the PowerPCPC7457; however, unless  
otherwise noted, all information here also applies to the PC7447. The PC7457 and  
PC7447 are implementations of the PowerPC microprocessor family of reduced  
instruction set computer (RISC) microprocessors. This document describes pertinent  
electrical and physical characteristics of the PC7457.  
Preliminary  
Specification  
α-site  
The PC7457 is the fourth implementation of the fourth generation (G4) microproces-  
sors from Motorola. The PC7457 implements the full PowerPC 32-bit architecture and  
is targeted at networking and computing systems applications. The PC7457 consists  
of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which sup-  
port a glueless backside L3 cache through a dedicated high-bandwidth interface. The  
PC7447 is identical to the PC7457 except it does not support the L3 cache interface.  
The core is a high-performance superscalar design supporting a double-precision  
floating-point unit and a SIMD multimedia unit. The memory storage subsystem sup-  
ports the MPX bus interface to main memory and other system resources. The L3  
interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private  
memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes  
may be used as cache; the remaining 2M bytes must be private memory.  
Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455  
application if the core power supply is 1.3V.  
Rev. 5345B–HIREL–02/04  

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