Datasheet > PCS5P23Z05D

PCS5P23Z05D

更新时间： 2024-11-28 05:59:59

品牌	Logo	应用领域
PULSECORE		/
页数	文件大小	规格书
14页	657K
描述
Multiple Output Timing-Safe™ Peak EMI reduction IC

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PCS5P23Z05D 数据手册

PCS5P23Z05D

PCS5P23Z09D

May 2007

rev 0.2

Multiple Output Timing-Safe™ Peak EMI reduction IC

General Features

the REF pin. The PLL feedback is on-chip and is obtained

from the CLKOUT pad.

•

Input frequency range: 100MHz to 150MHz

•

Clock distribution with Timing-Safe™ Peak EMI

Reduction

The PCS5P23Z09D has two banks of four outputs each,

which can be controlled by the Select inputs as shown in

the Select Input Decoding Table. The select input also

allows the input clock to be directly applied to the outputs

for chip and system testing purposes.

•

Zero input - output propagation delay

Multiple low-skew outputs

Output-output skew less than 250pS

Device-device skew less than 700pS

One input drives 9 outputs, grouped as

4 + 4 + 1(PCS5P23Z09D)

Multiple PCS5P23Z05D/09D devices can accept the same

input clock and distribute it. In this case the skew between

the outputs of the two devices is guaranteed to be less than

700pS.

•

One input drives 5 outputs (PCS5P23Z05D)

Less than 200 pS cycle-to-cycle jitter is compatible

with Pentium^®based systems

•

Available in 16pin 150-mil SOIC, 4.4 mm TSSOP

(PCS5P23Z09D), and in 8pin 150-mil SOIC,

4.4mm TSSOP package (PCS5P23Z05D)

3.3V operation

All outputs have less than 200pS of cycle-to-cycle jitter.

The input and output propagation delay is guaranteed to be

less than ±350pS, and the output to output skew is

guaranteed to be less than 250pS.

•

Advanced CMOS technology

The First True Drop-in Solution

Refer “Spread Spectrum Control and Input-Output Skew

Functional Description

Table”

for deviations and Input-Output skew for

PCS5P23Z05D/09D is a versatile, 3.3V zero-delay buffer

designed to distribute high-speed Timing-Safe™ clocks

with Peak EMI reduction. PCS5P23Z09D accepts one

reference input and drives out nine low-skew clocks. It is

available in a 16-pin package. The PCS5P23Z05D is the

eight-pin version of the PCS5P23Z09D. It accepts one

reference input and drives out five low-skew clocks.

All parts have on-chip PLLs that lock to an input clock on

PCS5P23Z05D and PCS5P23Z09D devices.

The PCS5P23Z05D/09D is available in two different

packages, as shown in the ordering information table.

Block Diagram

PLL

CLKOUT

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

MUX

REF

PLL

CLKOUT

REF

CLK1

CLK2

CLK3

Select Input

Decoding

PCS5P23Z05D

CLK4

PCS5P23Z09D

PulseCore Semiconductor Corporation

1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018

www.pulsecoresemi.com

Notice: The information in this document is subject to change without notice.

12 3 4 5 6 7...14

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与PCS5P23Z05D相关器件

型号	品牌	获取价格	描述	数据表
PCS5P23Z05DG-08-SR	PULSECORE	获取价格	Multiple Output Timing-Safe™ Peak EMI reducti
PCS5P23Z05DG-08-ST	PULSECORE	获取价格	Multiple Output Timing-Safe™ Peak EMI reducti
PCS5P23Z05DG-08-TR	PULSECORE	获取价格	Multiple Output Timing-Safe™ Peak EMI reducti
PCS5P23Z05DG-08-TT	PULSECORE	获取价格	Multiple Output Timing-Safe™ Peak EMI reducti
PCS5P23Z09AF-16-TR	PULSECORE	获取价格	PLL Based Clock Driver, 23Z Series, 8 True Output(s), 0 Inverted Output(s), PDSO8, 4.40 MM
PCS5P23Z09AG-16-ST	PULSECORE	获取价格	PLL Based Clock Driver, 23Z Series, 8 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 I
PCS5P23Z09AG-16-TR	PULSECORE	获取价格	PLL Based Clock Driver, 23Z Series, 8 True Output(s), 0 Inverted Output(s), PDSO8, 4.40 MM
PCS5P23Z09B	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
PCS5P23Z09BF-16-SR	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC
PCS5P23Z09BF-16-ST	PULSECORE	获取价格	Timing-Safe™ Peak EMI reduction IC

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