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PCS5P23Z05BG-08-ST PDF预览

PCS5P23Z05BG-08-ST

更新时间: 2024-11-28 05:59:59
品牌 Logo 应用领域
PULSECORE /
页数 文件大小 规格书
14页 659K
描述
Timing-Safe™ Peak EMI reduction IC

PCS5P23Z05BG-08-ST 技术参数

生命周期:Obsolete包装说明:0.150 INCH, GREEN, SOIC-16
Reach Compliance Code:unknown风险等级:5.84
系列:23Z输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G16长度:9.905 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:16
实输出次数:4最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
最小 fmax:50 MHzBase Number Matches:1

PCS5P23Z05BG-08-ST 数据手册

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May 2007  
rev 0.2  
PCS5P23Z05B/09B  
Timing-Safe™ Peak EMI reduction IC  
General Features  
eight-pin version and accepts one reference input and  
drives out five low-skew clocks.  
Clock distribution with Timing-Safe™ Peak EMI  
Reduction  
All parts have on-chip PLLs that lock to an input clock on  
the CLKIN pin. The PLL feedback is on-chip and is  
obtained from the CLKOUT pad, internal to the device.  
Input frequency range: 20MHz - 50MHz  
Zero input - output propagation delay  
Low-skew outputs  
Output-output skew less than 250pS  
Device-device skew less than 700pS  
Less than 200pS cycle-to-cycle jitter  
Available in 16pin, 150mil SOIC, 4.4mm TSSOP  
(PCS5P23Z09B), and in 8pin, 150 mil SOIC,  
4.4mm TSSOP Packages (PCS5P23Z05B)  
3.3V Operation  
Industrial temperature range  
Advanced CMOS technology  
The First True Drop-in Solution  
Multiple PCS5P23Z05B/09B devices can accept the same  
input clock and distribute it. In this case, the skew between  
the outputs of the two devices is guaranteed to be less than  
700pS.  
All outputs have less than 200pS of cycle-to-cycle jitter.  
The input and output propagation delay is guaranteed to be  
less than ±350pS, and the output-to-output skew is  
guaranteed to be less than 250pS.  
Refer Spread Spectrum Control and Input-Output Skew  
Functional Description  
Table”  
for deviations and Input-Output Skew for  
PCS5P23Z05B and PCS5P23Z09B devices  
PCS5P23Z05B/09B is a versatile, 3.3V zero-delay buffer  
designed to distribute high-speed Timing-Safe™ clocks  
with Peak EMI Reduction. PCS5P23Z09B accepts one  
reference input and drives out nine low-skew clocks. It is  
available in a 16pin Package. The PCS5P23Z05B is the  
The PCS5P23Z05B and PCS5P23Z09B are available in  
two different packages, as shown in the ordering  
information table.  
Block Diagram  
PLL  
CLKOUT  
CLKA1  
CLKA2  
CLKA3  
CLKA4  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
PLL  
CLKOUT  
MUX  
CLKIN  
CLKIN  
CLK1  
CLK2  
CLK3  
PCS5P23Z05B  
CLK4  
S2  
S1  
Select Input  
Decoding  
PCS5P23Z09B  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

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