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PCS5I23Z05AG-08-TT PDF预览

PCS5I23Z05AG-08-TT

更新时间: 2024-11-26 09:00:55
品牌 Logo 应用领域
PULSECORE 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 664K
描述
PLL Based Clock Driver, 23Z Series, 8 True Output(s), 0 Inverted Output(s), PDSO8, 4.40 MM, GREEN, TSSOP-8

PCS5I23Z05AG-08-TT 技术参数

生命周期:Obsolete包装说明:4.40 MM, GREEN, TSSOP-8
Reach Compliance Code:unknown风险等级:5.84
系列:23Z输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G8长度:5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:8
实输出次数:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
最小 fmax:20 MHzBase Number Matches:1

PCS5I23Z05AG-08-TT 数据手册

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March 2007  
rev 0.1  
PCS5P23Z05A/09A  
Low Frequency Timing-Safe™ Peak EMI reduction IC  
General Features  
available in a 16 pin Package. The PCS5P23Z05A is the  
eight-pin version and accepts one reference input and  
drives out five low-skew clocks.  
ƒ
Low Frequency Clock Distribution with Timing-  
SafePeak EMI Reduction  
Input frequency range: 4MHz - 20MHz  
Zero input - output propagation delay  
Low-skew outputs  
ƒ
ƒ
ƒ
All parts have on-chip PLLs that lock to an input clock on  
the XIN/CLKIN pin. The PLL feedback is on-chip and is  
obtained from the CLKOUT pad, internal to the device.  
ƒ
Output-output skew less than 250pS  
Device-device skew less than 700pS  
ƒ
Multiple PCS5P23Z05/09A devices can accept the same  
input clock and distribute it. In this case, the skew between  
the outputs of the two devices is guaranteed to be less than  
700pS.  
ƒ
ƒ
Less than 200pS Cycle-to-cycle jitter  
Available in 16pin, 150mil SOIC, 4.4mm TSSOP  
(PCS5P23Z09A), and in 8pin, 150 mil SOIC,  
4.4mm TSSOP Packages (PCS5P23Z05A).  
3.3V Operation  
ƒ
ƒ
All outputs have less than 200pS of Cycle-to-cycle jitter.  
The input and output propagation delay is guaranteed to be  
less than 350pS, and the output-to-output skew is  
guaranteed to be less than 250pS.  
Industrial temperature range  
ƒ
ƒ
Advanced 0.35µ CMOS technology  
The First True Drop-in Solution  
Functional Description  
Please refer Differential Cycle Slips and Spread Spectrum  
Control Table” for deviations and differential Cycle Slips  
for PCS5P23Z05A and PCS5P23Z09A devices  
PCS5P23Z05A/09A is a versatile, 3.3V Zero-delay buffer  
designed to distribute low frequency Timing-Safe™ clocks  
with Peak EMI Reduction. PCS5P23Z09A accepts one  
reference input and drives out nine low-skew clocks. It is  
Block Diagram  
PLL  
CLKOUT  
CLKA1  
CLKA2  
CLKA3  
CLKA4  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
MUX  
CLKIN  
PLL  
CLKOUT  
CLKIN  
CLK1  
CLK2  
CLK3  
S2  
S1  
Select Input  
Decoding  
PCS5P23Z05A  
CLK4  
PCS5P23Z09A  
PulseCore Semiconductor Corporation  
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018  
www.pulsecoresemi.com  
Notice: The information in this document is subject to change without notice.  

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