Datasheet > PCS1P2192A

PCS1P2192A

更新时间： 2024-11-04 05:59:55

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
7页	136K
描述
VDP Multiple Pixel Clock Generator

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中文翻译

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数据手册

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PCS1P2192A 数据手册

PCS1P2192A

VDP Multiple Pixel

Clock Generator

Features

• Generates multiple clock outputs from 20MHz

Product Description

The PCS1P2192A is a clock generator that generates

multiple selectable pixel clock outputs for Video Display

Panel applications from an external 20MHz reference

clock. The PLL based clock generator is specifically

designed to provide zero ppm frequency synthesis error

on all clock outputs. Various pixel clock rates are

selectable through frequency selection pins S[2:0] (Refer

to Frequency Selection Table) The device provides a

reference clock output additionally. Operating Supply

Voltage for this device is 3.3V ± 0.3V. The device is

available in an 8-pin SOIC package.

external reference clock

• Input frequency: 20MHz

• Output frequencies:

o Selectable CLKOUT:

108MHz, 27MHz, 33.2MHz, 85MHz, 65MHz,

25MHz, 45MHz, and 40MHz

o REFOUT: 20MHz

• Operating Supply Voltage: 3.3V ± 0.3V

• Zero ppm frequency synthesis error on all clock

outputs

Application

• 8-pin SOIC package

PCS1P2192A is targeted towards Video Display Panel

(VDP) applications like VGA, SVGA, XGA, WXGA,

UXGA.

Block Diagram

[S2: S0]

CLKOUT

REFOUT

CLKIN

PLL

GND

JANUARY 2010 – Rev. 2

Publication Order Number:

PCS1P2192/D

12 3 4 5 6 7

中文翻译

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