Datasheet > PCA9555_13

PCA9555_13

更新时间： 2022-03-04 04:29:17

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
34页	543K
描述
16-bit I2C-bus and SMBus I/O port with interrupt

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PCA9555_13 数据手册

PCA9555

16-bit I²C-bus and SMBus I/O port with interrupt

Rev. 08 — 22 October 2009

Product data sheet

1. General description

The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel

Input/Output (GPIO) expansion for I²C-bus/SMBus applications and was developed to

enhance the NXP Semiconductors family of I²C-bus I/O expanders. The improvements

include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O

conﬁguration, and smaller packaging. I/O expanders provide a simple solution when

additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.

The PCA9555 consists of two 8-bit Conﬁguration (Input or Output selection); Input, Output

and Polarity Inversion (active HIGH or active LOW operation) registers. The system

master can enable the I/Os as either inputs or outputs by writing to the I/O conﬁguration

bits. The data for each Input or Output is kept in the corresponding Input or Output

address compatible with the PCF8575, software changes are required due to the

enhancements, and are discussed in Application Note AN469.

The PCA9555 open-drain interrupt output is activated when any input state differs from its

corresponding input port register state and is used to indicate to the system master that

an input state has changed. The power-on reset sets the registers to their default values

and initializes the device state machine.

Three hardware pins (A0, A1, A2) vary the ﬁxed I²C-bus address and allow up to eight

devices to share the same I²C-bus/SMBus. The ﬁxed I²C-bus address of the PCA9555 is

the same as the PCA9554, allowing up to eight of these devices in any combination to

share the same I²C-bus/SMBus.

2. Features

I Operating power supply voltage range of 2.3 V to 5.5 V

I 5 V tolerant I/Os

I Polarity Inversion register

I Active LOW interrupt output

I Low standby current

I Noise ﬁlter on SCL/SDA inputs

I No glitch on power-up

I Internal power-on reset

I 16 I/O pins which default to 16 inputs

I 0 Hz to 400 kHz clock frequency

I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

12 3 4 5 6 7...34

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