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PC82573V

更新时间： 2024-11-15 20:02:23
品牌 Logo 应用领域
英特尔 - INTEL 时钟局域网数据传输PC外围集成电路
页数 文件大小 规格书
39页 467K
描述
LAN Controller, 1 Channel(s), 125MBps, CMOS, PBGA196, 15 X 15 MM, 1 MM, PITCH, LEAD FREE, TFBGA-196

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中文翻译

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PC82573V 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA, BGA196,14X14,40针数：196
Reach Compliance Code：compliantHTS代码：8542.31.00.01
风险等级：5.79地址总线宽度：
边界扫描：YES总线兼容性：PCI
最大时钟频率：25 MHz数据编码/解码方法：NRZ; NRZI; BIPH-LEVEL(MANCHESTER)
最大数据传输速率：125 MBps外部数据总线宽度：
JESD-30 代码：S-PBGA-B196JESD-609代码：e1
长度：15 mm低功率模式：YES
串行 I/O 数：1端子数量：196
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA196,14X14,40封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：260
电源：1.2,2.5,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Serial IO/Communication Controllers
最大供电电压：1.26 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：15 mm
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LANBase Number Matches：1

PC82573V 数据手册

 浏览型号PC82573V的Datasheet PDF文件第2页浏览型号PC82573V的Datasheet PDF文件第3页浏览型号PC82573V的Datasheet PDF文件第4页浏览型号PC82573V的Datasheet PDF文件第5页浏览型号PC82573V的Datasheet PDF文件第6页浏览型号PC82573V的Datasheet PDF文件第7页 
82573 Family of GbE Controllers  
Datasheet  
Product Features  
„ PCIe*  
— x1 PCIe* interface on ICH7 or MCH devices  
„ Manageability  
— Intel® Active Management Technology (Intel®  
AMT) support (82573E only)  
— Peak bandwidth: 2 Gb/s per direction  
— Power management  
— High bandwidth density per pin  
— Alerting Standards Format 2.0 and advanced  
pass through support (82573E/V only)  
— Boot ROM Preboot eXecution Environment  
(PXE) Flash interface support  
„ MAC  
— Optimized transmit and receive queues  
— IEEE 802.3x compliant flow control with  
software controlled pause times and threshold  
values  
— Compliance with PCI Power Management 1.1  
and Advanced Configuration and Power  
Interface (ACPI) 2.0 register set compliant  
— Wake on LAN support  
— Caches up to 64 packet descriptors per queue  
— Programmable host memory receive buffers  
(256 bytes to 16 KB) and cache line size (16  
bytes to 256 bytes)  
„ Additional  
— Three activity and link indication outputs that  
directly drive LEDs  
— Programmable LEDs  
— 32 KB configurable transmit and receive FIFO  
— Internal PLL for clock generation that can use  
buffer  
a 25 MHz crystal  
— Mechanism available for reducing interrupts  
generated by transmit and receive operation  
— Descriptor ring management hardware for  
transmit and receive  
— Power saving feature for the 82573L. During  
the L1 and L2 link states, the 82573L asserts  
the Clock Request signal (CLKREQ#) to  
indicate that its PCIe* reference clock can be  
gated  
— Optimized descriptor fetching and write-back  
mechanisms  
— On-chip power control circuitry  
— Loopback capabilities  
— Wide, pipelined internal data path architecture  
„ PHY  
— JTAG (IEEE 1149.1) Test Access Port (TAP)  
— Integrated PHY for 10/100/1000 Mb/s full and  
built in silicon  
half duplex operation  
„ Technology  
— IEEE 802.3ab auto negotiation support  
— IEEE 802.3ab PHY compliance and  
compatibility  
— Lead-free 196-pin Thin and Fine Pitch Ball Grid  
Array (TF-BGA) package  
— Operating temperature: 0° C to 70° C (with  
external regulators)  
— DSP architecture implements digital  
adaptive equalization, echo cancellation,  
and cross-talk cancellation  
— Operating temperature: 0° to 55° C (with on-  
die 2.5V regulator)  
— Storage temperature -40° C to 125° C  
„ Host Offloading  
— Transmit and receive IP, TCP and UDP  
checksum off-loading capabilities  
— Transmit TCP segmentation, IPv6 offloading,  
and advanced packet filtering  
— IEEE 802.1q VLAN support with VLAN tag  
insertion, stripping and packet filtering for up  
to 4096 VLAN tags  
— Descriptor ring management hardware for  
transmit and receive  
Order Number: 315514-002  
Revision 2.5  
1234567...39

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