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PBL386402SOT PDF预览

PBL386402SOT

更新时间: 2024-09-23 22:44:35
品牌 Logo 应用领域
爱立信 - ERICSSON /
页数 文件大小 规格书
16页 140K
描述
Subscriber Line Interface Circuit

PBL386402SOT 数据手册

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March 2000  
PBL 386 40/2  
Subscriber Line  
Interface Circuit  
Description  
Key Features  
The PBL 386 40/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated  
circuit for use in Digital Loop Carrier, FITL and other telecommunications equipment.  
The PBL 386 40/2 has been optimized for low total line interface cost and a high  
degree of flexibility in different applications.  
• 24-pin SSOP package  
• High and low battery with automatic  
switching  
• 65 mW on-hook power dissipation in  
active state  
The PBL 386 40/2 emulates resistive loop feed, programmable between 2x50 Ω  
and 2x900 , with short loop current limiting adjustable to max 45 mA. In the current  
limited region the loop feed is nearly constant current with a slight slope correspond-  
ing to 2x30 k.  
• On-hook transmission  
• Long loop battery feed tracks Vbat for  
maximum line voltage  
A second, lower battery voltage may be connected to the device to reduce short  
loop power dissipation. The SLIC automatically switches between the two battery  
supply voltages without need for external components or external control.  
The SLIC incorporates loop current, ground key and ring trip detection functions.  
The PBL 386 40/2 is compatible with both loop and ground start signaling.  
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is  
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or  
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable  
two-wire impedance, complex or real, is set by a simple external network.  
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the  
longitudinal balance specifications meet the DLC requirements.  
• Only +5 V feed in addition to battery  
• Selectable transmit gain (1x or 0.5x)  
• No power-up sequence  
• Programmable signal headroom  
• 43V open loop voltage @ -48V battery  
feed  
• Constant loop voltage for line leakage  
<5 mA (RLeak ~ >10 k@ -48V)  
The PBL 386 40/2 package options are 24-pin SSOP package, 24-pin SOIC and  
28-pin PLCC.  
• Full longitudinal current capability  
during on-hook state  
• Analog over temperature protection  
permits transmission while the  
protection circuit is active  
• Line voltage measurement  
• Polarity reversal  
Ring Relay  
RRLY  
Driver  
• Ground key detector  
DT  
• Tip open state with ring ground  
detector  
C1  
Ring Trip  
Comparator  
DR  
TIPX  
RINGX  
HP  
C2  
Input  
Decoder  
and  
C3  
• -40°C to +85°C ambient temperature  
range  
Ground Key  
Detector  
Control  
DET  
POV  
PSG  
PLC  
Line Feed  
Controller  
and  
Longitudinal  
Signal  
VCC  
Two-wire  
Interface  
Suppression  
LP  
L
PB  
VBAT2  
VBAT  
PBL 386 40/2  
386 40/2  
PLD  
REF  
Off-hook  
Detector  
PBL 386 40/2  
AGND  
BGND  
VTX  
RSN  
VF Signal  
Transmission  
24-pin SOIC, 24-pin SSOP, 28-pin PLCC  
PTG  
Figure 1. Block diagram.  
1

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