Datasheet > 可编程逻辑 > 可编程逻辑器件> PALCE22V10Z-25PI

PALCE22V10Z-25PI

更新时间： 2024-11-07 22:08:47

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
34页	662K
描述
24-Pin EE CMOS (Zero Power) Versatile PAL Device

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PALCE22V10Z-25PI 数据手册

PALCE22V10 COM'L: H-5/7/10/15/25,Q-10/15/25 IND: H-10/15/20/25

PALCE22V10Z COM'L: -25 IND: -15/25

PALCE22V10 and PALCE22V10Z

Families

24-Pin EE CMOS (Zero Power) Versatile PAL Device

DISTINCTIVE CHARACTERISTICS

As fast as 5-ns propagation delay and 142.8 MHz f

Low -pow er EE CMOS

(external)

MAX

10 macrocells programmable as registered or combinatorial, and active high or active low to

match application needs

Varied product term distribution allow s up to 16 product terms per output for complex

functions

Peripheral Component Interconnect (PCI) compliant (-5/-7/-10)

Global asynchronous reset and synchronous preset for initialization

Pow er-up reset for initialization and register preload for testability

Extensive third-party softw are and programmer support

24-pin SKINNY DIP, 24-pin SOIC, and 28-pin PLCC

5-ns and 7.5-ns versions utilize split leadframes for improved performance

GENERAL DESCRIPTION

The PALCE22V10 provides user-programmable logic for replacing conventional SSI/MSI gates and

ﬂip-ﬂops at a reduced chip count.

The PALCE22V10Z is an advanced PAL device built with zero-power, high-speed, electrically-

erasable CMOS technology. It provides user-programmable logic for replacing conventional zero-

power CMOS SSI/MSI gates and ﬂip-ﬂops at a reduced chip count.

The PALCE22V10Z provides zero standby power and high speed. At 30 µA maximum standby

current, the PALCE22V10Z allows battery-powered operation for an extended period.

The PAL device implements the familiar Boolean logic transfer function, the sum of products. The

PAL device is a programmable AND array driving a ﬁxed OR array. The AND array is programmed

to create custom product terms, while the OR array sums selected terms at the outputs.

The product terms are connected to the ﬁxed OR array with a varied distribution from 8 to16 across

the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each

macrocell can be programmed as registered or combinatorial, and active-high or active low. The

output conﬁguration is determined by two bits controlling two multiplexers in each macrocell.

Publication# 1 6564

Amendment/0

Rev: E

Issue Date: November 1 998

12 3 4 5 6 7...34

中文翻译

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与PALCE22V10Z-25PI相关器件

型号	品牌	获取价格	描述	数据表
PALCE22V10Z-25PI/4	LATTICE	获取价格	EE PLD, 25ns, CMOS, PDIP24,
PALCE22V10Z-25PI/5	LATTICE	获取价格	EE PLD, 25ns, CMOS, PDIP24,
PALCE22V10Z-25SC	LATTICE	获取价格	24-Pin EE CMOS (Zero Power) Versatile PAL Device
PALCE22V10Z-25SI	LATTICE	获取价格	24-Pin EE CMOS (Zero Power) Versatile PAL Device
PALCE22V10Z-25SI/4	LATTICE	获取价格	EE PLD, 25ns, CMOS, PDSO24,
PALCE22V10Z-25SI/5	LATTICE	获取价格	EE PLD, 25ns, CMOS, PDSO24,
PALCE24V10H-15JC	ETC	获取价格	Electrically-Erasable PLD
PALCE24V10H-15JC/4	LATTICE	获取价格	EE PLD, 15ns, CMOS, PQCC28,
PALCE24V10H-15PC	ETC	获取价格	Electrically-Erasable PLD
PALCE24V10H-15PC/4	LATTICE	获取价格	EE PLD, 15ns, CMOS, PDIP28,

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