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PALCE22V10-25LMB PDF预览

PALCE22V10-25LMB

更新时间: 2024-11-09 22:35:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 闪存可编程逻辑输入元件时钟
页数 文件大小 规格书
13页 350K
描述
Flash-erasable Reprogrammable CMOS PAL Device

PALCE22V10-25LMB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:LCC-28
针数:28Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.42其他特性:10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS
架构:PAL-TYPE最大时钟频率:30.3 MHz
JESD-30 代码:S-XQCC-N28JESD-609代码:e0
长度:11.43 mm专用输入次数:11
I/O 线路数量:10输入次数:22
输出次数:10产品条款数:132
端子数量:28最高工作温度:125 °C
最低工作温度:-55 °C组织:11 DEDICATED INPUTS, 10 I/O
输出函数:MACROCELL封装主体材料:UNSPECIFIED
封装代码:QCCN封装等效代码:LCC28,.45SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):240电源:5 V
可编程逻辑类型:FLASH PLD传播延迟:25 ns
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:1.9812 mm子类别:Programmable Logic Devices
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:11.43 mm
Base Number Matches:1

PALCE22V10-25LMB 数据手册

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PALCE22V10 is  
a replacement device for  
PALC22V10, PALC22V10B, and PALC22V10D.  
USE ULTRA37000TM FOR  
ALL NEW DESIGNS  
PALCE22V10  
Flash-erasable Reprogrammable  
CMOS PAL® Device  
• DIP, LCC, and PLCC available  
Features  
— 5 ns commercial version  
4 ns tCO  
Low power  
— 90 mA max. commercial (10 ns)  
— 130 mA max. commercial (5 ns)  
3 ns tS  
5 ns tPD  
181-MHz state machine  
• CMOS Flash EPROM technology for electrical erasabil-  
ity and reprogrammability  
— 10 ns military and industrial versions  
7 ns tCO  
6 ns tS  
• Variable product terms  
10 ns tPD  
110-MHz state machine  
— 2 ×(8 through 16) product terms  
• User-programmable macrocell  
— Output polarity control  
— 15-ns commercial, industrial, and military versions  
— 25-ns commercial, industrial, and military versions  
• High reliability  
— Individually selectable for registered or combina-  
torial operation  
— Proven Flash EPROM technology  
• Up to 22 input terms and 10 outputs  
— 100% programming and functional testing  
Logic Block Diagram (PDIP/CDIP)  
V
I
I
I
I
I
I
I
I
I
I
CP/I  
1
SS  
12  
11  
10  
9
8
7
6
5
4
3
2
PROGRAMMABLE  
AND ARRAY  
(132 X 44)  
8
10  
12  
14  
16  
16  
14  
12  
10  
8
Reset  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Preset  
13  
I
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
I/O  
9
I/O  
8
I/O  
7
I/O  
6
I/O  
5
I/O  
4
I/O  
3
I/O  
2
I/O  
1
I/O  
0
V
CC  
PLCC  
Top View  
LCC  
Top View  
Pin Configuration  
4
3
2
1
2827 26  
25  
4
3 2 1 282726  
I
I
I
5
6
7
8
9
10  
11  
25 I/O  
24 I/O  
23 I/O  
2
3
4
5
6
7
8
9
10  
11  
I
I
I/O  
I/O  
I/O  
2
3
4
24  
23  
22  
21  
20  
19  
I
NC  
I
I
I
22  
NC  
I
I
I
N/C  
N/C  
21 I/O  
20 I/O  
19 I/O  
5
6
7
I/O  
I/O  
I/O  
5
6
7
121314 1516 1718  
12131415161718  
Cypress Semiconductor Corporation  
Document #: 38-03027 Rev. *B  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised April 9, 2004  

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