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PALCE22V10-10JIT PDF预览

PALCE22V10-10JIT

更新时间: 2024-11-08 13:12:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 闪存
页数 文件大小 规格书
13页 387K
描述
Flash PLD, 10ns, CMOS, PQCC28, PLASTIC, LCC-28

PALCE22V10-10JIT 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.61Is Samacsys:N
其他特性:10 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK; VARIABLE PRODUCT TERMS最大时钟频率:76.9 MHz
JESD-30 代码:S-PQCC-J28长度:11.5316 mm
专用输入次数:11I/O 线路数量:10
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C组织:11 DEDICATED INPUTS, 10 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER可编程逻辑类型:FLASH PLD
传播延迟:10 ns认证状态:Not Qualified
座面最大高度:4.572 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:11.5316 mmBase Number Matches:1

PALCE22V10-10JIT 数据手册

 浏览型号PALCE22V10-10JIT的Datasheet PDF文件第2页浏览型号PALCE22V10-10JIT的Datasheet PDF文件第3页浏览型号PALCE22V10-10JIT的Datasheet PDF文件第4页浏览型号PALCE22V10-10JIT的Datasheet PDF文件第5页浏览型号PALCE22V10-10JIT的Datasheet PDF文件第6页浏览型号PALCE22V10-10JIT的Datasheet PDF文件第7页 
22V10  
PALCE22V10  
Flash Erasable,  
Reprogrammable CMOS PAL® Device  
5 ns tPD  
Features  
181-MHz state machine  
Low power  
10 ns military and industrial versions  
— 90 mA max. commercial (10 ns)  
— 130 mA max. commercial (5 ns)  
7 ns tCO  
6 ns tS  
10 ns tPD  
110-MHz state machine  
CMOS Flash EPROM technology for electrical erasabil-  
ity and reprogrammability  
15-ns commercial, industrial, and military versions  
25-ns commercial, industrial, and military versions  
High reliability  
Variable product terms  
2 x(8 through 16) product terms  
User-programmable macrocell  
Output polarity control  
Proven Flash EPROM technology  
100% programming and functional testing  
Individually selectable for registered or combinato-  
rial operation  
Functional Description  
Up to 22 input terms and 10 outputs  
DIP, LCC, and PLCC available  
The Cypress PALCE22V10 is a CMOS Flash Erasable sec-  
ond-generation programmable array logic device. It is imple-  
mented with the familiar sum-of-products (AND-OR) logic  
structure and the programmable macrocell.  
5 ns commercial version  
4 ns tCO  
3 ns tS  
Logic Block Diagram (PDIP/CDIP)  
V
I
I
I
I
I
I
I
I
I
I
CP/I  
1
SS  
12  
11  
10  
9
8
7
6
5
4
3
2
PROGRAMMABLE  
AND ARRAY  
(132 X 44)  
8
10  
12  
14  
16  
16  
14  
12  
10  
8
Reset  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Preset  
13  
I
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
I/O  
9
I/O  
8
I/O  
7
I/O  
6
I/O  
5
I/O  
4
I/O  
3
I/O  
2
I/O  
1
I/O  
0
V
CC  
PLCC  
Top View  
LCC  
Top View  
Pin Configuration  
CE22V101  
4
3
2
1
2827 26  
25  
4
3 2 1 282726  
I
I
I
5
6
7
8
9
10  
11  
25 I/O  
2
5
6
7
8
9
10  
11  
I
I
I/O  
I/O  
I/O  
2
3
4
24 I/O  
23 I/O  
3
4
N/C  
24  
23  
22  
21  
20  
19  
I
NC  
I
I
I
22  
NC  
I
I
I
N/C  
21 I/O  
20 I/O  
19 I/O  
5
6
7
I/O  
I/O  
I/O  
5
6
7
12131415161718  
121314 1516 1718  
CE22V103  
CE22V102  
PAL is a registered trademark of Advanced Micro Devices.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-03027 Rev. **  
Revised September 1996  

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