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PALCE20V8-15JIR PDF预览

PALCE20V8-15JIR

更新时间: 2024-09-20 13:12:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
14页 316K
描述
Flash PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28

PALCE20V8-15JIR 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.69其他特性:8 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
最大时钟频率:45.5 MHzJESD-30 代码:S-PQCC-J28
专用输入次数:12I/O 线路数量:8
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C组织:12 DEDICATED INPUTS, 8 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER可编程逻辑类型:FLASH PLD
传播延迟:15 ns认证状态:Not Qualified
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:J BEND端子位置:QUAD
Base Number Matches:1

PALCE20V8-15JIR 数据手册

 浏览型号PALCE20V8-15JIR的Datasheet PDF文件第2页浏览型号PALCE20V8-15JIR的Datasheet PDF文件第3页浏览型号PALCE20V8-15JIR的Datasheet PDF文件第4页浏览型号PALCE20V8-15JIR的Datasheet PDF文件第5页浏览型号PALCE20V8-15JIR的Datasheet PDF文件第6页浏览型号PALCE20V8-15JIR的Datasheet PDF文件第7页 
USE ULTRA37000TM FOR  
ALL NEW DESIGNS  
PALCE20V8  
Flash-Erasable Reprogrammable  
CMOS PAL® Device  
• QSOP package available  
Features  
— 10, 15, and 25 ns com’l version  
— 15, and 25 ns military/industrial versions  
• High reliability  
• Active pull-up on data input pins  
• Low power version (20V8L)  
— 55 mA max. commercial (15, 25 ns)  
— Proven Flash technology  
— 65 mA max. military/industrial  
(15, 25 ns)  
— 100% programming and functional testing  
• Standard version has low power  
Functional Description  
— 90 mA max. commercial  
(15, 25 ns)  
The Cypress PALCE20V8 is a CMOS Flash Erasable  
second-generation programmable array logic device. It is  
implemented with the familiar sum-of-product (AND-OR) logic  
structure and the programmable macrocell.  
— 115 mA max. commercial (10 ns)  
— 130 mA max. military/industrial (15, 25 ns)  
• CMOS Flash technology for electrical erasability and  
reprogrammability  
The PALCE20V8 is executed in a 24-pin 300-mil molded DIP,  
a 300-mil cerdip, a 28-lead square ceramic leadless chip  
carrier, a 28-lead square plastic leaded chip carrier, and a  
24-lead quarter size outline. The device provides up to 20  
inputs and 8 outputs. The PALCE20V8 can be electrically  
erased and reprogrammed. The programmable macrocell  
enables the device to function as a superset to the familiar  
24-pin PLDs such as 20L8, 20R8, 20R6, 20R4.  
• User-programmable macrocell  
— Output polarity control  
— Individually selectable for registered or combina-  
torial operation  
Logic Block Diagram (PDIP/CDIP/QSOP)  
GND  
I
10  
I
9
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
CLK/I  
0
12  
11  
10  
9
8
7
6
5
4
3
2
1
PROGRAMMABLE  
AND ARRAY  
(64 x 40)  
8
8
8
8
8
8
8
8
MUX  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
Macrocell  
MUX  
13  
OE/I  
14  
15  
I/O  
16  
I/O  
17  
I/O  
18  
I/O  
19  
I/O  
20  
I/O  
21  
I/O  
22  
I/O  
23  
24  
I
12  
I
13  
V
CC  
11  
0
1
2
3
4
5
6
7
Cypress Semiconductor Corporation  
Document #: 38-03026 Rev. *B  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised April 19, 2004  

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