PACVGA201Q

更新时间： 2024-11-03 22:16:03

品牌	Logo	应用领域
CALMIRCO		光电二极管
页数	文件大小	规格书
3页	131K
描述
VGA PORT COMPANION CIRCUIT

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中文翻译

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技术参数
数据手册

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PACVGA201Q 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	SSOP,
针数：	16	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.07
Is Samacsys：	N	模拟集成电路 - 其他类型：	ANALOG CIRCUIT
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
长度：	4.9 mm	功能数量：	1
端子数量：	16	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.75 mm
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	TIN LEAD
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3.895 mm	Base Number Matches：	1

PACVGA201Q 数据手册

CALIFORNIA MICRO DEVICES

PACVGA201

VGA PORT COMPANION CIRCUIT

Features

Pin Diagram

7 channels of ESD protection for all VGA port

connector pins meeting IEC-61000-4-2 Level-4 ESD

requirements (8KV contact discharge)

Very low loading capacitance from ESD protection

diodes on VIDEO lines, 4pF typical

TTL to CMOS level-translating buffers with power

down mode for HSYNC and VSYNC lines

Three power supplies for design flexibility

Compact 16-pin QSOP package

16-PIN QSOP PACKAGE

Product Description

The PACVGA201 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection

is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-61000-4-

2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current

pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.

Separate positive supply rails are provided for the VIDEO, DDC_OUT and SYNC channels to facilitate interfacing with low

voltage video controller ICs and provide design flexibility in multiple-supply-voltage environments.

An internal diode (D1, in schematic below) is provided such that V_CC2is derived from V_CC3. (V does not require an external

power supply input.) In applications where V_CC3may be powered down, diode D1 blocks ^Ca^Cn²y DC current path from the

DDC_OUT pins back to the powered down V_CC3rail via the upper ESD protection diodes.

Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).

These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V_CC3

When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current

from the V_CC3supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.

Schematic Diagram

C0651299

PAC VGA201 is a trademark of California Micro Devices Corp.

4/00

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

12 3

中文翻译

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