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PACVGA200Q PDF预览

PACVGA200Q

更新时间： 2024-09-28 22:16:03
品牌 Logo 应用领域
CALMIRCO 商用集成电路光电二极管
页数 文件大小 规格书
3页 134K
描述
VGA PORT COMPANION CIRCUIT

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PACVGA200Q 技术参数

生命周期：Transferred零件包装代码：SOIC
包装说明：SOP,针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.29商用集成电路类型：CONSUMER CIRCUIT
JESD-30 代码：R-PDSO-G24JESD-609代码：e0
长度：8.65 mm功能数量：1
端子数量：24最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE认证状态：Not Qualified
座面最大高度：1.75 mm表面贴装：YES
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：3.9116 mm
Base Number Matches：1

PACVGA200Q 数据手册

 浏览型号PACVGA200Q的Datasheet PDF文件第2页浏览型号PACVGA200Q的Datasheet PDF文件第3页 
CALIFORNIA MICRO DEVICES  
PACVGA200  
VGA PORT COMPANION CIRCUIT  
Features  
Pin Diagram  
• 7 channels of ESD protection for all VGA port  
connector pins meeting IEC-61000-4-2 Level-4 ESD  
requirements (8KV contact discharge)  
• Very low loading capacitance from ESD protection  
diodes on VIDEO lines, 4pF typical  
• TTL to CMOS level-translating buffers with power  
down mode for HSYNC and VSYNC lines  
• 75 Ω termination resistors for VIDEO lines (matched  
to 1% typ.)  
• Bi-directional level shifting N-channel FETs provided for  
DDC_CLK & DDC_DATA channels  
• Compact 24-pin QSOP package  
24-PIN QSOP PACKAGE  
Product Description  
The PACVGA200 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection  
is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-1000-4-  
2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current  
pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.  
Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage  
Video Controller ICs and provide design flexibility in multi-supply-voltage environments.  
Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).  
These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC4. These  
drivers have nominal 60Ω output impedance to match the characteristic impedance of the HSYNC & VSYNC lines of the video  
cables typically used in PC applications.  
Two N-channel FETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage  
than the monitor.  
Three 75Ω termination resistors suitable for terminating the video signals from the video DAC are also provided. These  
resistors have separate input pins to allow insertion of additional EMI filtering, if required, between the termination point and  
the ESD protection diodes. These resistors are matched to better than 2% for excellent signal level matching for the R/G/B  
signals.  
When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current  
from the VCC3 supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.  
An internal diode (D1 in schematic below) is also provided so that VCC3 can be derived from VCC4, if desired, by connecting V  
to V_BIAS. In applications where VCC4 may be powered down, diode D1 blocks any DC current paths from the DDC_OUT piCnCs3  
back to the powered down VCC4 rail via the top ESD protection diodes.  
Schematic Diagram  
© 2000 California Micro Devices Corp. All rights reserved. PACVGA200™ is a trademark of California Micro Devices Corp.  
C0641299  
4/00  
215 Topaz Street, Milpitas, California 95035  
Tel: (408) 263-3214  
Fax: (408) 263-7846  
www.calmicro.com  
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