PACVGA200

更新时间： 2024-11-03 22:16:03

品牌	Logo	应用领域
CALMIRCO		/
页数	文件大小	规格书
3页	134K
描述
VGA PORT COMPANION CIRCUIT

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PACVGA200 数据手册

CALIFORNIA MICRO DEVICES

PACVGA200

VGA PORT COMPANION CIRCUIT

Features

Pin Diagram

7 channels of ESD protection for all VGA port

connector pins meeting IEC-61000-4-2 Level-4 ESD

requirements (8KV contact discharge)

Very low loading capacitance from ESD protection

diodes on VIDEO lines, 4pF typical

TTL to CMOS level-translating buffers with power

down mode for HSYNC and VSYNC lines

75 Ω termination resistors for VIDEO lines (matched

to 1% typ.)

Bi-directional level shifting N-channel FETs provided for

DDC_CLK & DDC_DATA channels

Compact 24-pin QSOP package

24-PIN QSOP PACKAGE

Product Description

The PACVGA200 incorporates 7 channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection

is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-1000-4-

2 Level-4 ESD Protection (8KV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current

pulse is diverted via the protection diodes into the positive supply rail or ground where it may be safely dissipated.

Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage

Video Controller ICs and provide design flexibility in multi-supply-voltage environments.

Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC1, SYNC2).

These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and V_CC4. These

drivers have nominal 60Ω output impedance to match the characteristic impedance of the HSYNC & VSYNC lines of the video

cables typically used in PC applications.

Two N-channel FETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage

than the monitor.

Three 75Ω termination resistors suitable for terminating the video signals from the video DAC are also provided. These

resistors have separate input pins to allow insertion of additional EMI filtering, if required, between the termination point and

the ESD protection diodes. These resistors are matched to better than 2% for excellent signal level matching for the R/G/B

signals.

When the PWR_UP input is driven LOW the SYNC inputs can be floated without causing the SYNC buffers to draw any current

from the V_CC3supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW.

An internal diode (D1 in schematic below) is also provided so that V_CC3can be derived from V_CC4, if desired, by connecting V

to V_BIAS. In applications where V_CC4may be powered down, diode D1 blocks any DC current paths from the DDC_OUT pi^Cn^Cs³

back to the powered down V_CC4rail via the top ESD protection diodes.

Schematic Diagram

C0641299

4/00

215 Topaz Street, Milpitas, California 95035

Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

12 3

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与PACVGA200相关器件

型号	品牌	获取价格	描述	数据表
PACVGA200Q	CALMIRCO	获取价格	VGA PORT COMPANION CIRCUIT
PACVGA200QR	ONSEMI	获取价格	VGA Port Companion Circuit
PACVGA201	ONSEMI	获取价格	VGA Port Companion Circuit
PACVGA201	CALMIRCO	获取价格	VGA PORT COMPANION CIRCUIT
PACVGA201Q	CALMIRCO	获取价格	VGA PORT COMPANION CIRCUIT
PACVGA201QR	ONSEMI	获取价格	VGA Port Companion Circuit
PACVGA203	CALMIRCO	获取价格	VGA Port Companion Circuit
PACVGA203Q	CALMIRCO	获取价格	VGA Port Companion Circuit
PACVGA203QR	CALMIRCO	获取价格	VGA Port Companion Circuit
PACZIG1284	CALMIRCO	获取价格	IEEE 1284 Parallel Port ESD/EMI/Eermination network

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