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PACVGA105QR

更新时间： 2024-11-04 05:59:27
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管
页数 文件大小 规格书
9页 110K
描述
VGA Port Companion Circuit

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中文翻译

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PACVGA105QR 技术参数

是否无铅： 不含铅生命周期：End Of Life
零件包装代码：SOIC包装说明：SSOP,
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.04
模拟集成电路 - 其他类型：ANALOG CIRCUITJESD-30 代码：R-PDSO-G16
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：1功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin (Sn)
端子形式：GULL WING端子节距：0.64 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
宽度：3.895 mmBase Number Matches：1

PACVGA105QR 数据手册

 浏览型号PACVGA105QR的Datasheet PDF文件第2页浏览型号PACVGA105QR的Datasheet PDF文件第3页浏览型号PACVGA105QR的Datasheet PDF文件第4页浏览型号PACVGA105QR的Datasheet PDF文件第5页浏览型号PACVGA105QR的Datasheet PDF文件第6页浏览型号PACVGA105QR的Datasheet PDF文件第7页 
VGA Port Companion Circuit  
PACVGA105  
Features  
Product Description  
•
Seven channels of ESD protection designed to  
meet IEC-1000-4-2 Level-4 ESD requirements  
( 8kV contact discharge)  
Very low loading capacitance from ESD  
protection diodes at less than 5pF typical  
TTL to CMOS level-translating buffers for the  
HSYNC and VSYNC lines  
The PACVGA105 incorporates 7 channels of ESD  
protection for signal lines commonly found in a VGA  
port for PCs. ESD protection is implemented with  
current steering diodes designed to safely handle the  
high peak surge currents associated with the IEC-  
1000-4-2 Level-4 ESD Protection Standard ( 8kV  
•
•
•
Three independent supply pins (VCC, VRGB and  
contact discharge). When the channels are subjected  
to an electrostatic discharge, the ESD current pulse  
is diverted via the protection diodes into the positive  
supply rails or ground where they may be safely  
dissipated.  
VAUX) to facilitate operation with sub-micron  
Graphics Controller ICs  
High impedance pull-ups (50kΩ nominal to VAUX  
for HSYNC and VSYNC inputs  
Pull-up resistors (1.8kΩ nominal to VCC) for  
DDC_CLK and DDC_DATA lines  
Compact 16-pin QSOP package  
Lead-free version available  
•
•
)
•
•
The upper ESD diodes for the R, G and B channels  
are connected to a separate supply rail (VRGB) to  
facilitate interfacing to graphics controller ICs with low  
voltage supplies. The remaining channels are  
connected to the main 5V rail (VCC). The lower diodes  
for the R, G and B channels are also connected to a  
dedicated ground pin (GNDA) to minimize crosstalk  
due to common ground impedance.  
Applications  
•
ESD protection and termination resistors for VGA  
(video) port interfaces  
Desktop PCs  
Notebook computers  
LCD monitors  
•
•
•
Two non-inverting buffers are also included in this IC  
for buffering the HSYNC and VSYNC signals from  
the graphics controller IC. These buffers will accept  
TTL input levels and convert them to CMOS output  
levels that swing between GND and VCC. These  
drivers have a nominal 60Ω output impedance to  
match the characteristic impedance of the HSYNC  
and VSYNC lines of the video cables typically used.  
The inputs of these drivers also have high impedance  
pull-ups (50kW nom.) pulling up to the VAUX rail. In  
addition, the DDC_CLOCK and DDC_DATA  
channels have 1.8kΩ resistors pulling these inputs  
up to the main 5V (VCC) rail.  
©2010 SCILLC. All rights reserved.  
May 2010 Rev. 2  
Publication Order Number:  
PACVGA105/D  
1234567...9

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