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PACKTELE8101FS

更新时间: 2024-11-12 23:26:07
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2页 140K
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Smart Packet Telephony 8101

PACKTELE8101FS 数据手册

 浏览型号PACKTELE8101FS的Datasheet PDF文件第2页 
Freescale Semiconductor, Inc.  
Fact Sheet  
SMART NETWORK  
DESIGNS  
SMART PACKET  
TELEPHONY 8101  
interfaces to the packet network; is designed to provide a  
UTOPIA level-2 interface and H.100 TDM interface; and is  
designed to run essential application-specific protocols  
required by the target application.  
As the communications industry migrates from circuit-switched to packet-centric  
infrastructure, equipment manufacturers require systems solutions that include  
comprehensive design tools, signal processing, the ability to interface with both  
packet- and circuit-switched networks, control and signaling functions, and  
software support.  
The DSP subsystem is designed to run essential signal  
processing functions for voice, fax and modem data  
applications. At the heart of the DSP subsystem are six  
MSC8101 DSPs in a PTMC form factor. Typical functions  
include voice compression, DTMF detection, voice activity  
detection, echo cancellation and silence suppression, as  
well as modem and fax data modulation and  
demodulation. The DSP subsystem interfaces to the  
MPC8260 baseboard via the MSC8101’s 60x bus. The  
POTS subsystem connects to the DSP subsystem, and it  
offers four narrow-band T1/E1 TDM ports. The POTS  
subsystem is also designed to support four analog  
POTS ports for direct interfaces to standard analog  
voice terminals, and it provides a TDM stream for the  
DSP array.  
The first in a series of integrated, yet flexible, packet telephony system solutions from  
Motorola, Smart Packet Telephony 8101 is a hardware reference design for medium-size  
media gateway equipment that can handle voice, fax or modem data services.  
The reference platform and development kit are ultimately designed to give  
manufacturers of remote access servers (RAS) and IP-PBXs that are based on MSC8100  
DSPs a significant time-to-market advantage. At the front end of the design process,  
system architects may use this scalable evaluation platform to assess the capabilities  
of the StarCore® architecture-based MSC8100 DSPs and establish suitability for their  
end product. Since it is a comprehensive hardware reference design, it is also designed  
to facilitate rapid system development. Multiple third parties supply media gateway and  
remote access server software to complete the packet telephony solution.  
The development platform includes support for voice compression and echo cancellation,  
essential for voice-over-packet systems. Smart Packet Telephony 8101 consists of three  
main subsystems. The MPC8260 baseboard is designed to support Fast Ethernet  
Reference Design Overview (with future expansion cards)  
Dual  
Ethernet  
PHY  
SDRAM  
MPC8260*  
60x bus  
Linux®  
SDRAM  
RS232  
UTOPIA  
H.100  
Connector  
TDM  
FPGA  
Timeslot  
Switch  
OC3 or DSL  
Framer and  
PHY  
MSC8101  
MSC8101  
Quad E1/  
T1 Framer  
Codec  
MSC8101  
MSC8101  
MSC8101  
MSC8101  
MSC8101 Card  
MSC8102 Card  
Future Expansion Card  
ATM  
4x POTS  
4x E1/T1  
(not initially implemented)  
* The MPC8260 contains a PowerPC® processor core.  
For More Information On This Product,  
Go to: www.freescale.com  

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