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PA7572P-20L

更新时间： 2024-09-12 20:16:59
品牌 Logo 应用领域
美台 - DIODES 光电二极管
页数 文件大小 规格书
10页 345K
描述
EE PLD, 20ns, PLA-Type, CMOS, PDIP40, 0.600 INCH, LEAD FREE, DIP-40

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PA7572P-20L 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP40,.6
针数：40Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.28
Is Samacsys：N架构：PLA-TYPE
最大时钟频率：66.6 MHzJESD-30 代码：R-PDIP-T40
JESD-609代码：e3长度：52.07 mm
专用输入次数：12I/O 线路数量：24
输入次数：24输出次数：24
产品条款数：124端子数量：40
最高工作温度：70 °C最低工作温度：
组织：12 DEDICATED INPUTS, 24 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP40,.6封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
可编程逻辑类型：EE PLD传播延迟：20 ns
认证状态：Not Qualified子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：15.24 mmBase Number Matches：1

PA7572P-20L 数据手册

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To find out if the package you need is  
available, contact Customer Service  
PA7572 PEEL Array™  
Programmable Electrically Erasable Logic Array  
Versatile Logic Array Architecture  
CMOS Electrically Erasable Technology  
- Reprogrammable in 40-pin DIP, 44-pin PLCC and  
TQFP packages  
- 24 I/Os, 14 inputs, 60 registers/latches  
- Up to 72 logic cell output functions  
- PLA structure with true product-term sharing  
- Logic functions and registers can be I/O-buried  
Flexible Logic Cell  
- Up to 3 output functions per logic cell  
- D,T and JK registers with special features  
- Independent or global clocks, resets, presets,  
clock polarity and output enables  
High-Speed Commercial and Industrial Versions  
- As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX  
)
- Industrial grade available for 4.5 to 5.5V VCC and -40  
- Sum-of-products logic for output enables  
to +85 °C temperatures  
Development and Programmer Support  
- ICT PLACE Development Software  
- Fitters for ABEL, CUPL and other software  
- Programming support by popular third-party  
programmers  
Ideal for Combinatorial, Synchronous and  
Asynchronous Logic Applications  
- Integration of multiple PLDs and random logic  
- Buried counters, complex state-machines  
- Comparators, decoders, other wide-gate functions  
General Description  
The PA7572 is a member of the Programmable Electrically The PA7572’s logic and I/O cells (LCCs, IOCs) are  
Erasable Logic (PEEL™) Array family based on Anachip’s extremely flexible with up to three output functions per cell  
CMOS EEPROM technology. PEEL™ Arrays free (a total of 72 for all 24 logic cells). Cells are configurable as  
designers from the limitations of ordinary PLDs by D, T, and JK registers with independent or global clocks,  
providing the architectural flexibility and speed needed for resets, presets, clock polarity, and other features, making  
today’s programmable logic designs. The PA7572 offers a the PA7572 suitable for a variety of combinatorial,  
versatile logic array architecture with 24 I/O pins, 14 input synchronous and asynchronous logic applications. The  
pins and 60 registers/latches (24 buried logic cells, 12 input PA7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx)  
registers/latches, 24 buried I/O registers/latches). Its logic and 66.6MHz (fMAX) at moderate power consumption  
array implements 100 sum-of-products logic functions 140mA (100mA typical). Packaging includes 40-pin DIP  
divided into two groups each serving 12 logic cells. Each and 44-pin PLCC (see Figure 1). Anachip and popular  
group shares half (60) of the 120 product-terms available.  
third-party development tool manufacturers provide  
development and programming support for the PA7572.  
Figure 1. Pin Configuration  
Figure 2. Block Diagram  
DIP (600 mil)  
2 Input/  
PLCC  
Global Clock Pins  
I/CLK1  
I
VCC  
I
I
1
2
3
4
5
6
7
8
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
6
5 4 3 2 1 44 43 42 41 40  
Global  
I
I
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
7
8
9
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
Cells  
124 (62X2)  
Array Inputs  
true and  
I
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
10  
11  
12  
13  
14  
15  
16  
17  
Input  
Cells  
(INC)  
2
complement  
12 Input Pins  
I/O  
Cells  
(IOC)  
9
24 I/O Pins  
24  
24  
12  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
I/O  
GND  
Buried  
logic  
I/CLK  
VCC  
I
Global Cells  
18 19 20 21 22 23 24 25 26 27 28  
Logic  
Array  
I
Logic  
Logic  
A
B
C
D
I
I
I
I
functions  
Control  
Cells  
I/O Cells  
24  
24  
to I/O cells  
Input Cells  
I
I
I
I
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
(LCC)  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/CLK2  
4 sum terms  
5 product terms  
for Global Cells  
24 Logic Control Cells  
up to 3 output functions per cell  
(72 total output functions  
possible)  
96 sum terms  
(four per LCC)  
44 43 42 41 4039 38 37 36 35 34  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
GND  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
TQFP  
9
10  
11  
GND  
I
12 13 14 151617 18 19 20 21 22  
I
I
I
I
Logic Control Cells  
08-15-002A  
PA7572  
GND  
I/CLK2  
08-15-001A  
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights  
under any patent accompany the sale of the product.  
Rev. 1.0 Dec 16, 2004  
1/10  
1234567...10

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PA-758-102A-R1- NIDEC

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