PA7536 PEEL Array™
Programmable Electrically Erasable Logic Array
Versatile Logic Array Architecture
CMOS Electrically Erasable Technology
- Reprogrammable in 28-pin DIP, SOIC and PLCC
packages
- 12 I/Os, 14 inputs, 36 registers/latches
- Up to 36 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and
other wide-gate functions
- Sum-of-products logic for output enables
Development and Programmer Support
- Anachip WinPLACE Development Software
- Fitters for ABEL and other software
- Programming support by popular third-party
programmers
High-Speed Commercial and Industrial Versions
- As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX
)
- Industrial grade available for 4.5 to 5.5V VCC and
-40 to +85 °C temperatures
General Description
The PA7536 is a member of the Programmable Electrically independent or global clocks, resets, presets, clock
Erasable Logic (PEEL™) Array family based on ICT’s polarity, and other special features, making the PA7536
CMOS EEPROM technology. PEEL™ Arrays free suitable for a variety of combinatorial, synchronous and
designers from the limitations of ordinary PLDs by asynchronous logic applications. The PA7536 offers pin
providing the architectural flexibility and speed needed for compatibility and super-set functionality to popular 28-pin
today’s programmable logic designs. The PA7536 offers a PLDs, such as the 26V12. Thus, designs that exceed the
versatile logic array architecture with 12 I/O pins, 14 input architectures of such devices can be expanded upon. The
pins and 36 registers/latches (12 buried logic cells, 12 PA7536 supports speeds as fast as 9ns/15ns (tpdi/tpdx)
Input registers/latches and 12 buried registers/latches). Its and 83.3MHz (fMAX) at moderate power consumption
logic array implements 50 sum-of-products logic functions 105mA (75mA typical). Packaging includes 28-pin DIP,
that share 64 product terms. The PA7536’s logic and I/O SOIC, and PLCC (see Figure 1). Development and
cells (LCCs, IOCs) are extremely flexible offering up to programming support for the PA7536 is provided by
three output functions per cell (a total of 36 for all 12 logic Anachip and popular third-party development tool
cells). Cells are configurable as D, T, and JK registers with manufacturers.
Figure 1. Pin Configuration
Figure 2. Block Diagram
I/CLK1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
I/CLK2
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2 Input/
I/CLK1
I/CLK2
I/O
2
I
Global Clock Pins
I
I
I
I
3
I
I/O
Global
Cells
4
I
I/O
5
I
I/O
76 (38X2)
Array Inputs
true and
6
I
I/O
7
VCC
I/O
I
8
I
I
I
I
I
I
I
GND
I/O
Input
Cells
(INC)
2
complement
VCC
9
12 Input Pins
10
11
12
13
14
I/O
I
I
I
I
I
I
I
I/O
Cells
(IOC)
I/O
12 I/O Pins
9
I/O
12
12
12
10
11
12
13
14
I/O
I/O
I/O
I/O
I/O
I/O
Buried
logic
SOIC
I/CLK1
I/CLK2
Global Cells
Logic
Array
I
I
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
Logic functions
to I/O cells
Logic
A
B
C
D
Control
Cells
12
12
I/O Cells
DIP
I
I
I
Input Cells
4
3
2
1
28 27 26
(LCC)
I
I
I/O
I/O
I/O
I/O
GND
I/O
I/O
5
6
7
8
9
10
11
25
24
23
22
21
20
19
2 sum terms
3 product terms
for Global Cells
VCC
12 Logic Control Cells
up to 3 output functions per cell
(36 total output functions possible)
48 sum terms
(four per LCC)
VCC
I
I
I
I
I
I
I
I
I
I
I
Logic Control Cells
12 13 14 15 16 17 18
08-16-002A
PA7536
PLCC
08-16-001A
1
04-02-052A
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