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P89LPC903 PDF预览

P89LPC903

更新时间: 2024-10-25 22:26:07
品牌 Logo 应用领域
恩智浦 - NXP 微控制器
页数 文件大小 规格书
55页 1125K
描述
8-bit microcontrollers with two-clock 80C51 core 1 kB 3 V Flash with 128-byte RAM

P89LPC903 数据手册

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P89LPC901/902/903  
8-bit microcontrollers with two-clock 80C51 core  
1 kB 3 V Flash with 128-byte RAM  
Rev. 04 — 21 November 2003  
Product data  
1. General description  
The P89LPC901/902/903 are single-chip microcontrollers in low-cost 8-pin packages,  
based on a high performance processor architecture that executes instructions in two  
to four clocks, six times the rate of standard 80C51 devices. Many system-level  
functions have been incorporated into the P89LPC901/902/903 in order to reduce  
component count, board space, and system cost.  
2. Features  
2.1 Principal features  
1 kB byte-erasable Flash code memory organized into 256-byte sectors and  
16-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile  
data storage.  
128-byte RAM data memory.  
Two 16-bit counter/timers. (P89LPC901 Timer 0 may be configured to toggle a  
port output upon timer overflow or to become a PWM output.)  
23-bit system timer that can also be used as a Real-Time clock.  
Two analog comparators (P89LPC902 and P89LPC903, single analog  
comparator on P89LPC901).  
Enhanced UART with fractional baudrate generator, break detect, framing error  
detection, automatic address detection and versatile interrupt capabilities  
(P89LPC903).  
High-accuracy internal RC oscillator option allows operation without external  
oscillator components. The RC oscillator option is selectable and fine tunable.  
2.4 V to 3.6 V VDD operating range with 5 V tolerant I/O pins (may be pulled up or  
driven to 5.5 V). Industry-standard pinout with VDD, VSS, and reset at locations 1,  
8, and 4.  
Up to six I/O pins when using internal oscillator and reset options.  
8-pin SO-8 package.  
2.2 Additional features  
A high performance 80C51 CPU provides instruction cycle times of 167 ns to  
333 ns for all instructions except multiply and divide when executing at 12 MHz.  
This is six times the performance of the standard 80C51 running at the same  
clock frequency. A lower clock frequency for the same performance results in  
power savings and reduced EMI.  
In-Application Programming (IAP-Lite) and byte erase allows code memory to be  
used for non-volatile data storage.  

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