Datasheet > P75N02LTG

P75N02LTG

更新时间： 2024-11-18 05:59:19

品牌	Logo	应用领域
其他 - ETC		晶体晶体管场效应晶体管
页数	文件大小	规格书
3页	31K
描述
N-Channel Logic Level Enhancement Mode Field Effect Transistor

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中文翻译

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数据手册

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P75N02LTG 数据手册

P75N02LTG

TO-220

N-Channel Logic Level Enhancement

Mode Field Effect Transistor

NIKO-SEM

Lead-Free

PRODUCT SUMMARY

1. GATE

2. DRAIN

3. SOURCE

V_(BR)DSS

R_DS(ON)

I_D

5mΩ

75A

ABSOLUTE MAXIMUM RATINGS (T_C= 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS SYMBOL

Gate-Source Voltage V_GS

LIMITS

UNITS

±20

T_C= 25 °C

Continuous Drain Current

I_D

T_C= 100 °C

Pulsed Drain Current¹

Avalanche Current

I_DM

I_AR

170

Avalanche Energy

L = 0.1mH

L = 0.05mH

T_C= 25 °C

T_C= 100 °C

E_AS

E_AR

140

Repetitive Avalanche Energy²

5.6

Power Dissipation

P_D

32.75

-55 to 150

275

Operating Junction & Storage Temperature Range

Lead Temperature (¹/₁₆” from case for 10 sec.)

T, T_stg

°C

T_L

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

Junction-to-Case

SYMBOL

TYPICAL

MAXIMUM

UNITS

R_qJC

R_qJA

R_qCS

2.3

Junction-to-Ambient

62.5

°C / W

Case-to-Heatsink

0.6

¹Pulse width limited by maximum junction temperature.

²Duty cycle £ 1％

ELECTRICAL CHARACTERISTICS (T_C= 25 °C, Unless Otherwise Noted)

LIMITS

PARAMETER

SYMBOL

TEST CONDITIONS

STATIC

UNIT

MIN TYP MAX

Drain-Source Breakdown Voltage

Gate Threshold Voltage

Gate-Body Leakage

V_(BR)DSS

V_GS(th)

I_GSS

V_GS= 0V, I_D= 250mA

V_DS= V_GS, I_D= 250mA

1.5

V_DS= 0V, V_GS= ±20V

±250 nA

V_DS= 20V, V_GS= 0V

250

Zero Gate Voltage Drain Current

I_DSS

V_DS= 20V, V_GS= 0V, T_J= 125 °C

Sep-09-2004

12 3

中文翻译

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