Datasheet > P75N02LD

P75N02LD

更新时间： 2024-11-18 05:59:19

品牌	Logo	应用领域
其他 - ETC		晶体晶体管场效应晶体管
页数	文件大小	规格书
3页	115K
描述
N-Channel Logic Level Enhancement Mode Field Effect Transistor

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中文翻译

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P75N02LD 数据手册

N-Channel Logic Level Enhancement

Mode Field Effect Transistor

P75N02LD

NIKO-SEM

TO-252 (D²PAK)

PRODUCT SUMMARY

1. GATE

V_(BR)DSS

R_DS(ON)

I_D

2. DRAIN

3. SOURCE

75A

5mΩ

ABSOLUTE MAXIMUM RATINGS (T_C= 25 °C Unless Otherwise Noted)

PARAMETERS/TEST CONDITIONS

SYMBOL

LIMITS

UNITS

Gate-Source Voltage

V_GS

±20

T_C= 25 °C

Continuous Drain Current

I_D

T_C= 100 °C

Pulsed Drain Current¹

Avalanche Current

I_DM

I_AR

170

Avalanche Energy

L = 0.1mH

L = 0.05mH

T_C= 25 °C

T_C= 100 °C

E_AS

E_AR

140

5.6

Repetitive Avalanche Energy²

Power Dissipation

P_D

Operating Junction & Storage Temperature Range

Lead Temperature (¹/₁₆” from case for 10 sec.)

T_j, T_stg

T_L

-55 to 150

275

°C

THERMAL RESISTANCE RATINGS

THERMAL RESISTANCE

SYMBOL

TYPICAL

MAXIMUM

UNITS

Junction-to-Case

2.3

R_θJC

R_θJA

R_θCS

Junction-to-Ambient

Case-to-Heatsink

62.5

°C / W

0.6

¹Pulse width limited by maximum junction temperature.

²Duty cycle ≤ 1％

ELECTRICAL CHARACTERISTICS (T_C= 25 °C, Unless Otherwise Noted)

LIMITS

PARAMETER

SYMBOL

TEST CONDITIONS

STATIC

_GS= 0V, I_D= 250µA

_DS= V_GS, I_D= 250µA

UNIT

MIN TYP MAX

Drain-Source Breakdown Voltage

Gate Threshold Voltage

Gate-Body Leakage

V_(BR)DSS

V_GS(th)

I_GSS

1.5

V_DS= 0V, V_GS= ±20V

V_DS= 20V, V_GS= 0V

±250 nA

Zero Gate Voltage Drain Current

I_DSS

µA

V_DS= 20V, V_GS= 0V, T_J= 125 °C

250

AUG-02-2001

12 3

中文翻译

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