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P701-10DC PDF预览

P701-10DC

更新时间: 2024-02-15 08:09:18
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描述
Low EMI Spread Spectrum Multiplier IC (in Die or Package)

P701-10DC 数据手册

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PLL701-10  
Low EMI Spread Spectrum Multiplier IC (in Die or Package)  
FEATURES  
PACKAGE PIN CONFIGURATION  
Spread Spectrum Clock Generator/Multiplier with  
output selectable from 1x to 8x.  
XIN/FIN  
XOUT/SD0*^  
M2^  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
GND  
13MHz to 240MHz output with output enable.  
13MHz to 30 MHz reference input frequency  
accepted from crystal or external clock signal.  
Reduced EMI from Spread Spectrum Modulation,  
with selectable modulation amplitude for Center  
Spread, Down Spread or Asymmetric Spread.  
TTL/CMOS compatible outputs.  
3.3V Operating Voltage.  
150 ps maximum cycle-to-cycle jitter.  
Available in 16-Pin 150mil SSOP or DIE.  
AVDD  
REF/SD1*^  
VDD  
M1^  
M0^  
SC3^  
SC0^  
OE^  
SC1^  
FOUT  
GND  
SC2^  
XIN/FIN = 10 ~ 30 MHz  
DESCRIPTION  
DIE PAD CONFIGURATION  
The PLL701-10 is a low EMI Clock Generator and  
Multiplier for high-speed digital systems. It uses  
Spread Spectrum Technology (SST) and permits  
different levels of EMI reduction by selecting the  
amplitude of the applied SST. The SST feature can  
be turned off. An output enable input is also used.  
The chip operates with input frequencies ranging from  
13 to 30 MHz and provides 1x to 8x at its output.  
69 mil  
1700, 2540  
AVDD  
18  
XOUT/SD0*^  
GNDOSC  
23  
25  
22  
21  
20  
19  
C501A  
A0404  
-04A  
17  
16  
AVDD  
REF/SD1*^  
OUTPUT CLOCK (FOUT) SELECTION  
15  
14  
VDD  
VDD (optional)  
28  
M2^  
M1^  
M0^  
29  
30  
FIN/XIN  
(MHz)  
FOUT  
(MHz)  
13  
12  
VDD (optional)  
SC3^  
M2  
M1  
M0  
Multiplier  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
13 ~ 28  
13 ~ 28  
14 ~ 30  
13 ~ 28  
20 ~ 30  
17 ~ 30  
15 ~ 30  
13 ~ 28  
X1  
X2  
X3  
X4  
X5  
X6  
X7  
X8  
13 ~ 28  
26 ~ 56  
10  
OE^  
42 ~ 90  
52 ~ 112  
100 ~ 150  
102 ~ 180  
105 ~ 210  
104 ~ 224  
8
7
FOUT  
34  
35  
SC0^  
SC1^  
1
4
5
6
GNDBUF  
Y
X
BLOCK DIAGRAM  
Note: ^: Internal pull-up resistor (120kfor SD0, 30 kfor SC0-  
SC2, SD1, M0-M2 and OE). The internal pull-up resistor  
results in a default high value when no pull-down resistor is  
connected to this pin.  
OE  
XIN  
PLL  
SST  
XTAL  
OSC  
FOUT  
XOUT  
*: SD0 and SD1 are latched upon power-up.  
M(0:2)  
SD(0:1)  
SC(0:3)  
Control  
Logic  
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1  

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