Datasheet > P580-30DC

P580-30DC

更新时间： 2024-09-24 03:43:47

品牌	Logo	应用领域
PLL		振荡器石英晶振压控振荡器
页数	文件大小	规格书
9页	251K
描述
38MHz-640MHz Low Phase Noise VCXO

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中文翻译

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数据手册

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P580-30DC 数据手册

(Preliminary) PL580-30

38MHz-640MHz Low Phase Noise VCXO

FEATURES

DIE CONFIGURATION

•

Less than 0.4ps RMS (12KHz-20MHz) phase

jitter for all frequencies.

Low phase noise output (@ 1MHz frequency

offset

65 mil

•

∗

-140dBc/Hz for 311.04MHz,

-131dBC/Hz for 622.08MHz

(1550,1475)

24 23 22 21

GNDBUF

CMOS

•

19MHz-40MHz crystal input.

38MHz-640MHz output.

XIN

Die ID:

Selectable PECL, LVDS, or CMOS outputs.

No external varicap required.

Output Enable selector.

Wide pull range (+/-200ppm).

3.3V operation.

2222-22A

LVDSB

PECLB

XOUT

SEL2

VDDBUF

DNC

Available in 3x3 QFN or 16-pin TSSOP

packages.

PECL

OE_CTRL

VCON

C502A

LVDS

DESCRIPTION

OE_SEL^

The PL580-30 is a monolithic low jitter and low

phase noise VCXO, capable of 0.4ps RMS phase

jitter and PECL, LVDS, or CMOS outputs, covering a

wide frequency output range up to 640MHz. It allows

the control of the output frequency with an input

voltage (VCON), using a low cost crystal.

The PL580-30 is designed to address the demanding

requirements of high performance applications such

as SONET, GPS, XDSL, etc.

(0,0)

Note1: ^ Denotes internal pull up resistor.

DIE SPECIFICATIONS

Name

Value

62 x 65 mil

GND

Size

Reverse side

Pad dimensions

Thickness

80 micron x 80 micron

10 mil

BLOCK DIAGRAM

VCON

VCO

Divider

VARICAP

Charge

Output

QBAR

VCO

(F_XiNx16)

Pump

XIN

Phase

Detector

XTAL

OSC

Divider

Loop

(1,2,4,8)

XOUT

Filter

Performance Tuner

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 1

12 3 4 5 6 7...9

中文翻译

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