Datasheet > P4NA40FI

P4NA40FI

更新时间： 2024-09-21 09:56:35

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		晶体晶体管
页数	文件大小	规格书
10页	200K
描述
N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

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P4NA40FI 数据手册

STP4NA40

STP4NA40FI

N - CHANNEL ENHANCEMENT MODE

FAST POWER MOS TRANSISTOR

TYPE

V_DSS

R_DS(on)

I_D

STP4NA40

STP4NA40FI

400 V

< 2 Ω

4 A

2.8 A

■

TYPICAL R_DS(on)= 1.7 Ω

± 30V GATE TO SOURCE VOLTAGE RATING

100% AVALANCHE TESTED

REPETITIVE AVALANCHE DATA AT 100^oC

LOW INTRINSIC CAPACITANCES

GATE GHARGE MINIMIZED

REDUCED THRESHOLD VOLTAGE SPREAD

TO-220

ISOWATT220

DESCRIPTION

This series of POWER MOSFETS represents the

most advanced high voltage technology. The

optimized cell layout coupled with

a new

proprietary edge termination concur to give the

device low R_DS(on)and gate charge, unequalled

ruggedness and superior switching performance.

INTERNAL SCHEMATIC DIAGRAM

APPLICATIONS

■

HIGH CURRENT, HIGH SPEED SWITCHING

SWITCH MODE POWER SUPPLIES (SMPS)

DC-AC CONVERTERS FOR WELDING

EQUIPMENT AND UNINTERRUPTIBLE

POWER SUPPLIES AND MOTOR DRIVE

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

STP4NA40

STP4NA40FI

V_DS

V_{DG R}

V_GS

I_D

Drain-source Voltage (V_GS= 0)

Drain-gate Voltage (R_GS= 20 kΩ)

Gate-source Voltage

Drain Current (continuous) at T_c= 25 ^oC

Drain Current (continuous) at T_c= 100 ^oC

Drain Current (pulsed)

400

± 30

2.5

2.8

1.7

I_D

I_DM(•)

P_tot

Total Dissipation at T_c= 25 ^oC

W/^oC

^oC

Derating Factor

0.64

0.32

2000

V_ISO

T_stg

T_j

Insulation Withstand Voltage (DC)

Storage Temperature

-65 to 150

150

Max. Operating Junction Temperature

(•) Pulse width limited by safe operating area

1/10

November 1996

12 3 4 5 6 7...10

中文翻译

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