Datasheet > 存储 > SRAM> P4C167L-35PMB

P4C167L-35PMB

更新时间： 2024-11-21 03:54:07

品牌	Logo	应用领域
PYRAMID		/
页数	文件大小	规格书
10页	192K
描述
ULTRA HIGH SPEED 16K X 1 STATIC CMOS RAMS

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中文翻译

获取价格

数据手册

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P4C167L-35PMB 数据手册

P4C167/P4C167L

ULTRA HIGH SPEED 16K X 1

STATIC CMOS RAMS

FEATURES

Full CMOS, 6T Cell

Separate Data I/O

High Speed (Equal Access and Cycle Times)

– 10/12/15/20/25 ns (Commercial)

– 12/15/20/25/35 ns (Industrial)

Three-State Output

TTL Compatible Output

Fully TTL Compatible Inputs

Standard Pinout (JEDEC Approved)

– 15/20/25/35/45 ns (Military)

Low Power Operation

Single 5V±10% Power Supply

– 20-Pin 300 mil DIP

– 20-Pin 300 mil SOJ

– 20-Pin LCC

Data Retention with 2.0V Supply (P4C167L

Military)

DESCRIPTION

Access times as fast as 10 nanoseconds are available,

greatlyenhancingsystemspeeds.CMOSreducespower

consumption to low levels.

The P4C167/L are 16,384-bit high speed static RAMs or-

ganizedas16Kx1.TheCMOSmemoriesrequirenoclocks

orrefreshingandhaveequalaccessandcycletimes. The

RAMs operate from a single 5V ± 10% tolerance power

supply. Data integrity is maintained for supply voltages

downto2.0V, typicallydrawing10µA.

TheP4C167/Lareavailablein20-pin300milDIP, 20-pin

300 mil SOJ, and 20-pin LCC packages providing excel-

lentboardleveldensities.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

LCC (L9)

DIP (P2, C6)

SOJ (J2) SIMILAR

Document # SRAM106 REV A

Revised October 2005

12 3 4 5 6 7...10

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