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P4C167L-35LMB PDF预览

P4C167L-35LMB

更新时间: 2024-11-25 03:54:07
品牌 Logo 应用领域
PYRAMID /
页数 文件大小 规格书
10页 192K
描述
ULTRA HIGH SPEED 16K X 1 STATIC CMOS RAMS

P4C167L-35LMB 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.14
最长访问时间:35 nsJESD-30 代码:R-CQCC-N20
JESD-609代码:e0长度:10.922 mm
内存密度:16384 bit内存集成电路类型:STANDARD SRAM
内存宽度:1功能数量:1
端子数量:20字数:16384 words
字数代码:16000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:16KX1封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装形状:RECTANGULAR
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
筛选级别:MIL-STD-883 Class B座面最大高度:1.905 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.4295 mm
Base Number Matches:1

P4C167L-35LMB 数据手册

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P4C167/P4C167L  
ULTRA HIGH SPEED 16K X 1  
STATIC CMOS RAMS  
FEATURES  
Full CMOS, 6T Cell  
Separate Data I/O  
High Speed (Equal Access and Cycle Times)  
– 10/12/15/20/25 ns (Commercial)  
– 12/15/20/25/35 ns (Industrial)  
Three-State Output  
TTL Compatible Output  
Fully TTL Compatible Inputs  
Standard Pinout (JEDEC Approved)  
– 15/20/25/35/45 ns (Military)  
Low Power Operation  
Single 5V±10% Power Supply  
– 20-Pin 300 mil DIP  
– 20-Pin 300 mil SOJ  
– 20-Pin LCC  
Data Retention with 2.0V Supply (P4C167L  
Military)  
DESCRIPTION  
Access times as fast as 10 nanoseconds are available,  
greatlyenhancingsystemspeeds.CMOSreducespower  
consumption to low levels.  
The P4C167/L are 16,384-bit high speed static RAMs or-  
ganizedas16Kx1.TheCMOSmemoriesrequirenoclocks  
orrefreshingandhaveequalaccessandcycletimes. The  
RAMs operate from a single 5V ± 10% tolerance power  
supply. Data integrity is maintained for supply voltages  
downto2.0V, typicallydrawing10µA.  
TheP4C167/Lareavailablein20-pin300milDIP, 20-pin  
300 mil SOJ, and 20-pin LCC packages providing excel-  
lentboardleveldensities.  
FUNCTIONAL BLOCK DIAGRAM  
PIN CONFIGURATIONS  
LCC (L9)  
DIP (P2, C6)  
SOJ (J2) SIMILAR  
Document # SRAM106 REV A  
Revised October 2005  
1

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